Hello,
I have a couple of questions about the LO power in AWR1243 from a cascaded design perspective.
1. What is the output power level of the 20 GHz LO out when the chip is a multi-chip master ?
2. What is the maximum and minimum LO power level requirement to drive the slave chips ? I recall minimum being -10 dBm but I cannot find where I read it.
Thank you,
RJ