TMP103: Data Hold Time

Are you asking about the Max value of HDDAT in Section 6.6 Timing Requirements?

The HDDAT max value is calculated based on the specified max SCL Frequency. It doesn't apply to lower frequencies, and is only shown here to mimic the NXP I2C Specification document.

Thanks,
Ren

>> Are you asking about the Max value of HDDAT in Section 6.6 Timing Requirements?
Yes.

When SCL frequency is 100-kHz, is the tHDDAT to be extending more than 400-nsec?

Regards,
ACGUY

Hi Ren,

I measured the tHDDAT at SCL = 400kHz.

Please see the attached file.

Why it over the 400nsec?

Vdd = 3.3V

Pullup Resistor = 1.5kohm

Regards,

ACGUY

Many of the I2C specifications can be applied to both the Master and Slave at different instances during the transaction. The NXP I2C Specification doesn't clearly describe when a specification should be applied to the Master and when it should be applied to the Slave. See www.nxp.com/.../UM10204.pdf

Most likely, the Master has control of this timing. The Slave device (TMP103) only controls SDA when it is performing ACK or during read transaction. I can't verify which clock cycle is represented in your image, so I can't tell who is in control.

HDDAT Max is not a parameter that directly impacts our device's operation. TMP103 will work correctly with the timing shown, as long as other timing requirements are met. For example, excessive HDDAT would not cause a problem until it became so long as to prevent SUDAT minimum from being met. Since Frequency is specified but duty cycle for the clock is not, there is a very broad range of valid timing parameters.

Thanks,
Ren

I know that the "400-nsec over" is not be causes of problems for I2C spec.

I would like to ask is why tHDDAT exceeds 400 nsec.