OPT9221: Lack of output data

Viktor,

Please check I2C register 'minor', which is DE register 0x01, bit [4:0] and see what it reads.  If it reads 30, then try the below register sequence to start-up streaming:

// Initialization sequence for OPT9221
//
// RegAddr is (slaveID << 16) + RegisterAddress
// Translate internally as needed
// OPT9221_RegWrite(RegAddr, RegValue)
//
// The following sequence will bring up OPT9221 with 4 quads, 4 subframes, 9% integration at 20 fps, 48 MHz modulation frequency, no dealiasing
// and with (1280 bytes * 240 lines) DVP output with horizontal blank period of 1280 bytes
//
OPT9221_RegWrite(0x5880, 0x000001); // tg_dis = 1
OPT9221_RegWrite(0x5C3C, 0x005000); // blk_size = 1280
OPT9221_RegWrite(0x5C3D, 0x005000); // blk_blank_size = 1280
// Configure blk_blank_size as needed by the receiving chip
OPT9221_RegWrite(0x5C3F, 0x00000A); // fb_ready_en = 0
OPT9221_RegWrite(0x5882, 0x0249F0); // pix_cnt_max = 150000
OPT9221_RegWrite(0x5C4C, 0x800006); // intg_duty_cycle = 6
OPT9221_RegWrite(0x5880, 0x000000); // tg_dis = 0

// Modulation Frequency settings: default of 48 MHz
OPT9221_RegWrite(0x580C, 0x100000); // mod_m1 = 16, mod_m_frac1 = 0
OPT9221_RegWrite(0x580F, 0x00049A); // mod_n1 = 2, mod_ps1 = 1
OPT9221_RegWrite(0x5802, 0x00001C); // mod_pll_update = 1
msleep(10); // 10ms delay - very conservative
OPT9221_RegWrite(0x5802, 0x000018); // mod_pll_update = 0

// Optional: Set phy_test_enable to get a deterministic test pattern each frame.
// This is useful to test the output interface during bringup
// The test pattern in bytes is 0, 0, 1, 2, 3, ..., 254, 255, 0, 1, 2, ...
// Note the two leading 0s at the start of the frame

OPT9221_RegWrite(0x5C29, 0x304042); // phy_test_enable = 1
// Uncomment the next line to clear it
//OPT9221_RegWrite(0x5C29, 0x304040); // phy_test_enable = 0