AWR1243: Test Pattern Generation Configuration

Which version of Radar Studio are you using?

Thank you
Cesar

I am using Radar Studio v1.9.1.0 with mmwave_dfp_00_09_01_06

Hello Dustin,
Please find my reply below:

1)TestPattern Gen Timing -> In the documentation it states that samples are output at the System Clock of 200 MHz. How does this relate to data clock / frame clock. Inside my fpga logic the frame clock is 9.375 MHz but I cannot determine how this is governed.

<TI> In the regular radar operation the ADC data generating by the ADC sampling rate is sent over LVDS. One sample corresponds to 1 set complex data (I and Q ) on each of the RX channels. But in the LVDS test pattern mode there is no ADC samples. The equivalent "sampling " to decide the how fast the input data is generated is governed by the 200Mhz internal clock. If you select this parameter as 50 for example, the data is generated at 200/50 =4Mhz rate. This is similar to using 4Msps ADC rate. Its not related to the frame clock.

2) TestPattern Pkt Size -> In the documentation it states that valid range is 64 - 1024 (4 RX complex), 64 - 2048 (4 RX real), 64 - 2048 (2 RX complex), and 64 - 4096 (2 Rx real). However in radar studio I cannot set a value greater then 255.

<TI> We will check this and get back. I think this was fixed in the latest radar studio package (DFP 1.0)

3) Value Rollover -> I have included some graphics below. My first test had different starting and increment values but I could not make sense of what was coming across the line, so I simplified to have one channel I values increment and all the rest be zero. When I receive the data the RX3 I channel increments by 1 but it restarts back at 0 after reaching a count of 7.

4) Random Values -> I have attached a chipscope plot data after shift register, and a hex editor view of data collected (hex editor data is packed RX0-3 I, RX0-3 Q). Again RX0-2 I/Q are all zeros but RX3 Q seems to be a random starting value and it random toggles to a different value.

<TI> The TestApttern Gen Timing is set to a very high sampling rate which the LVDS cannot handle. The data rate should be kept much lesser than the LVDS output rate so that all the data can be transferred out before it gets over written. In your example you are setting 200Msps with complex 4 channels. ie will give a data rate of 25600 Mbits/sec. But the LVDS rate (4 lanes) is only 600*4=2400Mbits/sec. So you need to reduce the sampling clock rate.

Regards,
Vivek

Vivek,

Thank you for your response.  DFP 1.0 fixed issue #2.   With regards to 1, 3, and 4 please see below.

From your explanation for issue #1, is the test pattern generator just about filling the LVDS FIFO (CBUFF)? Is it up to the user to configure the test pattern generator such that and overflow and / or underflow condition does not occur on the chip?  For instance, if I set the LVDS to 900 mbps but configure the test pattern generation to be something very low such as 1 msps (200 / 200) then does an underflow occur?  Will the LVDS valid flag be deasserted?  Will the LVDS Frame/Data clock still continue?

--Dustin