RTOS/IWR1642: Interface of external RF switch to increase number of transmit antennas

Hi,

The chirp start interrupt can be found under packages/ti/common/sys_common/sys_common_xwr16xx_mss.h SOC_XWR16XX_MSS_CHIRP_START_INT. We didn't use the interrupt in our sdk mmw demo as you have already figured. But this interrupt can be hooked up on MSS and control GPIO.

Thanks and Regards,
Michelle

Thank you for your reply.

1. Does this interrupt event gets generated at the start of each chirp? If yes do you have any thoughts on the time delay we will experience while routing it to the GPIO through MSS. Also is it a hardware or software triggered interrupt ?

2. Another related question: If we are using two transmitters on IWR1642 then how the switching between two transmitters is happening from a software perspective. Is MSS issuing a command to do it? In other words is there a signal which is switching the transmitter? Also, does the chirp interrupt signal have any link with that signal or not?

For 1, the interrupt is issued by BSS and handled by MSS software. As to the source of interrupt and latency, I'll need to check with the BSS expert on that and get back to you.

For 2, the transmitter switching is taken care of by BSS. The configuration has specs for the chirp profile and the sequence. We don’t have signal from mss to switch the transmitter.

Regards,
Michelle

Hello Rashid,
Could you please elaborate your use-case further?

While you response with detailed info about use-case, let me explain device capability in context of this scenario.

1. FIRST OF ALL IWR1642 DOESN'T SUPPORT CASCADE MODE. You can have two IWR1642 together but they can't be synchronized as both device need to have same LO (signal) for syncing.
2. You can trigger frame at both device using HW pulse (SYNC_IN) where both devices use their own 2-Tx to transmit but processing on both devices may have different result as source of RF is not same/synchronized.
3. MSS gets chirp interrupt but that is actually chirp-available-interrupt, i.e. when ADC data is sampled and stored in ADCBuffer memory this interrupt is generated to MSS/DSS.
4. GPIO based syncing may not be stable solution.


Regards,
Jitendra

Hi Jitendra,

Thank you for your detailed reply.

Our application details: We ideally want to use a single chip (IWR1642), but extend the number of transmit antennas to have a bigger virtual array (16 in our case accomplished using 4 Tx antennas and 4 Rx antennas). One way to do it will be to take one of Tx output lines (which connects to the antenna currently) and put an external RF switch (4x1). That way after the switch we can have 4 Tx antennas. By optimally placing these 4 Tx antennas and 4 Rx antennas we shall be able to make a virtual array of 16 elements.

However, in order to do so, we need to control the RF switch appropriately. In other words, at chirp 1, the switch shall connect to Tx1, at chirp 2 to Tx 2, at chirp 3 to Tx 3, and then at chirp 4 to Tx4, and so on. Our thought was that if we can get the chirp start signal from the IWR1642 hardware or software as a trigger then we can do a simple logic to do a 2 bit counter and then control the RF switch using GPIO lines. 

1. From Michelle's  reply above SOC_XWR16XX_MSS_CHIRP_START_INT can be used for that purpose. But based on your comment, it looks like that this interrupt happens after the chirp data is available as compared to start of the chirp ?  

2. Is there a way to get an interrupt signal at the start of Chirp ( like Chirp start signal or Tx on signal) ?

3. You mentioned GPIO based syncing may not be stable. Can you elaborate that a little further based on our application explained above?

4. Based on question 1, if we can get the chirp start signal, then do you see any other issues/limitations with our approach ?

Thanks.

Hi Jitendra,

Were you able to get a chance to look into my above message ?

Thanks.