RTOS/IWR1642: How to make us level delay

You can go through SYSBIOS for this using the Timestamp module. This Timestamp module of SYSBIOS will use the C674X CPU time stamp registers (TSCL (low 32-bit), TSCH (high 32-bit) that clock at the DSP speed of 600 MHz. These registers are directly accessible using the compiler also as long as c6x.h is included in the referring C code. For inline delays (i.e CPU waiting during the time) of less than 7 seconds (2^32/600e6), TSCL alone is sufficient. The SDK uses this non-SYSBIOS way for cycle profiling purposes in the out of box demo, the function used is Cycleprofiler_getTimeStamp() which is simply a macro that equates to TSCL (so no function call/return overhead from the user) and is implemented in the header file ti/utils/cycleprofiler/cycle_profiler.h. So if you are using the SDK, you can write code like below (not verified, you can check):

#include <ti/utils/cycleprofiler/cycle_profiler.h>

static inline void delay(uint32_t ticks)

{

volatile uint32_t startTimeStamp;

volatile uint32_t currentTimeStamp;

startTimeStamp = Cycleprofiler_getTimeStamp();

do {

currentTimeStamp = Cycleprofiler_getTimeStamp();

} while ((currentTimeStamp - startTimeStamp) < ticks);

}

...

Uint32 interruptState;

interruptState = _disable_interrupts(); //this function is supported directly by the TI C674x compiler

GPIO = 1;

delay(10 * 600); //DSP speed is 600 MHz

GPIO = 0;

_restore_interrupts(interruptState); //this function is supported directly by the TI C674x compiler

If you want to use SYSBIOS, you may want to see the thread . This is essentially same implementation as one without SYSBIOS, but it is better in the sense that you can use SYSBIOS API to know the CPU frequency instead of hard-coding what is known.