I am in the process of designing the system power supply for a device that included the AFE58JD28. In the datasheet (under NDA) section 11.1, figure 122 the timing of the power supply initialization is shown. I do not clearly understand the relationships between t1, t2, and t3. None of these value are exactly defined, and t1 and t3 are shown as having the same end points.
- I am assuming t1 is the allowable rise time of DVDD_1P2.
- I am assuming t2 is the allowable rise time of all other supplies. (?)
- I am assuming t3 is the allowable delay between enabling supplies.
Questions:
- Is t2 only specifying the allowed rise time of the noted supplied, or is it trying to indicate maximum DVDD_1P2 valid to the other supplies being vaild?
- Under the note, is t3 < t1 correct? Based on text I was expecting this to read t3 > t1.
- Based on the text, is it adequate to assure DVDD_1P2 > AVDD_1P8 while DVDD_1P2 < 1.2V, or should AVDD_1P8 be 0V while DVDD_1P2 < 1.2V
- Are there any power supply sequencing requirement during power down?
Thanks, Chip Weller
