AWR1243: Fanout Clock Buffer for cascaded sytem

Hi Koki,

This reference design is still in development. We are still working on the full release for the Cascaded AWR reference design. The part we have used on our current design is an IDT 5PB1104. But we are now evaluating the TI LMK00804B.

For the digital sync input voltage depends on the selected AWR1243 digital I/O voltage selected depending on if the VIOIN is powered with 1.8V or 3.3V. But For the 40MHz clock synchronization, OSC_CLKOUT output is fixed to a single-ended 1.3V output. This is described in the  AWR1243 Cascade application note: http://www.ti.com/lit/an/swra574a/swra574a.pdf 

Always recommend planning for terminations to make the signal as clean as possible. No need for a pull-up/down.

Other than the datasheet specifications of the above parts, we do not have a published clock distribution requirement specification at this time.

I hope this helps for now. Let me know if that answered all of your questions on this topic.

Thanks,
Randy

Hi Randy,

Thank you for the speedy reply.

As same as your comment, I was considering use of 5PB1204 (@VDD = 1.8V) for OSC_CLKOUT.
And 5PB1214 (@VDD = 3.3V) will be used for SYNC_OUT, since VIOIN is applied 3.3 V.

Your answer provided resolved my issue.
Thanks a lot!

BR,

Koki Tanji

Hi Koki, please see my above changes. I had originally left out the different buffer properties of the OSC_CLKOUT pins vs. the digital sync pins.

Thanks,
Randy