AFE5801 have no LVDS signal output,
My design is as follows:
1、The difference clock is generated by FPGA PLL，ac couple to CLKP pin and CLKM ping .Vpp is 3.3V（and later attempt reduced voltage to 1.8v, but to no avail）
When I does not connect the external CLK, there is a common voltage in CLKP pin and CLKM pin.The two voltages are the same . It is 1.56V. The supply voltage 3.3V and 1.8V are fine,
2、pin DCLKP and DCLKM have a common voltage,about 0.75v, others LVDS port voltage is about 0.23v.
3、Serial interface register write and read is OK.
4、register value like is:
reg0 ->0
reg1 ->0000(03FC)
reg2 ->E000(E3F8)
reg3 ->0000
reg4 ->0008
reg7 ->0002
Q1:Whether the chip is damaged or not?
Q2:Whether the register is configured correctly？
Q3:There are other registers that need to be configured?
thanks，
Best Wishes,
