PGA460-Q1: PGA460-Q1 communication io

Hi Shin,

1. Yes, a PGA460 bus can be used in UART or USART (SPI) mode at 3.3V or 5V logic level operation for direct connection to a single external MCU. Up to eight PGA460 can occupy a single USART bus. In the PGA460-Q1 device, the last 3-bits of the command field are reserved for UART address information. The address information in the command field is compared to the UART_ADDR parameter in the EEPROM memory where the UART address is programmed. Upon receiving the command field, the PGA460-Q1 device checks if the self-address matches the received address and if it matches, the device executes on the received command. If the address does not match, the device disregards the received frame. For improved communication efficiency, common broadcast commands are defined where the PGA460-Q1 device executes regardless of the address in the command field.
The PGA460-Q1 TEST pin serves multiple purposes including:
• Allows the user to extract internal signals from the PGA460-Q1 device.
• Selects the output voltage of the digital pins which enables a 3.3-V MCU or a 5-V MCU to be connected to the device without using any external voltage translators. The RXD, TXD, SCLK, DECPL, and TEST pins are affected by this selection.
The digital voltage-level selection performed by the TEST pin is executed at device power up. On power-up, the device checks the level of the TEST pin. If the level is low, the digital output pins operate at 3.3 V. If the TEST pin is tied high (3.3 V or 5 V are both considered high state), the digital output pins operate at a 5 V. This condition is latched in the PGA460-Q1 device so that the test mux can further use the TEST pin as previously described. If the application requires that a 5-V digital output is used and a test mux output must be extracted from the PGA460-Q1 device, then a weak pullup resistor on the TEST pin can be connected as shown in Figure 42 of the PGA460 datasheet.
As shown in Figure 42, the resistor (RPU) is connected to a permanent power supply and a current path to ground is generated through the RPU resistor and the 800-kΩ internal resistance. This configuration is no problem for the system; however, it might cause a small quiescent-current increase in applications that require the use of the PGA460-Q1 low-power mode to preserve energy. In this case, the TEST pin can be connected to a GPIO pin on the external MCU that can output a logic low or high state on the TEST pin to select the voltage level at device start-up and later disable the GPIO output to preserve energy or reconfigure the GPIO as an input in case the MCU uses any of the PGA460-Q1 test output signals. The external pullup resistor is only required for CMOS 5-V UART communication and is not required for 3-V communication.

2. Yes, the PGA460's IO pin can be connected to a LIN bus, but the PGA460 does not support the LIN protocol. Instead, the IO pin supports One-Wire UART (OWU) which is "LIN-like" for bus topology. TCI can only be used in a start topology. The PGA460-Q1 device implements an option to connect the UART interface on the IO pin. In this case, the UART interface becomes a battery-voltage one-wire interface (OWI) because the IO pin is an open-drain type and implements a 10-kΩ pullup to the VPWR pin. This feature is possible because the communication on the UART interface is unidirectional at all times.
To enable the one-wire UART interface the IO_IF_SEL bit must be set to 1, in which case the internal communication multiplexers connect the digital logic of the UART interface to the IO-pin transceiver. The RXD and TXD pins are not changed and their operation is preserved.
Although UART communication through the IO pin, RXD pin, and TXD pin is allowed simultaneously, a possibility can occur for data collision in the case when the master controller is communicating to the IO pin while another master-controlled is trying to communicate through the UART transceiver on the RXD and TXD pins. Therefore, in an application where the IO pin is used, the RXD pin must be connected to the Hi-Z state which would cause the UART transceiver to disable when the PGA460-Q1 device has been enabled. For a detailed explanation, see the Interface Description section of the datasheet.