Hi,
Is there a way to disable the 40MHz OSC_CLKOUT signal (pin A14) while allow the chip to operate in the multichip master mode (cascading configuration)?
Thanks ,
Dom
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Hi,
Is there a way to disable the 40MHz OSC_CLKOUT signal (pin A14) while allow the chip to operate in the multichip master mode (cascading configuration)?
Thanks ,
Dom
Hi Dom,
The 40 MHz clock fanout from the master device is meant only as a BOM reduction mechanism and there is no delay match requirement on the 40MHz clock domain. The chirp frame sync triggers will implicitly align the ADC output data domains and CSI transfers as they recover the mixed IF return data. So functionality should not be impacted by having each slave device on its own 40MHz source.
However, the AWR1243 firmware ICD does include DOES NOT INCLUDE a way to isolate the cascading functionality to exclude the OSC_CLKOUT functionality. Your design should be free to terminate the output on the PCB and ignore it.
Please let me know if that answers your questions on this topic.
Thank you,
Randy
Hi Randy,
I couldn't find an API call in the AWR1243 firmware ICD Revision 0.95 to solely exclude the OSC_CLKOUT functionality while leaving the CASCADING_CFG as MULTICHIP_MASTER. Would you be so kind and point me to that section please?
Thank you,
Dom