PGA450-Q1: EEPROM wiped on power cycling

Hi Jon,

We’ve replicated Armon's power profile condition at the VPWR pin. Although the EEPROM is not resetting, we did notice some of the ESFRs toggling at random when the device is taken in and out of reset after the +1000 power cycle test. Note: the units we have tested have not been OTP programmed (factory devices).

We continue to suspect the issue is due to weakly programmed EEPROM. If the power cycling/reset event is forcing an EEPROM programming routine, we recommend that the EE_STATUS bit be polled after each power-up cycle to check if the EE_CTRL's WRITE bit is unintentionally triggered.

Additional information that would be helpful to our continued testing:
1. What is the voltage at the TXD and RXD pins throughout the power profile? We’d like to ensure we are forcing the same voltage at these pins since we do not have the exact hardware to replicate the UART pull-up behavior.
2. After power cycling the device +1000 times, do the customer's ESFR values change at all at device start-up?

Hi Akeem,

Thanks for the reply.

Interesting, if the ESFRs are toggling at random then there is a possibility that EE_CTRL could be set by mistake. We will include this in our tests to see if we experience this.

Please keep me updated should there be any further resolution to the issue.

Regards,
Jon