IWR1443: CSI Frame Structure

Antonio Puglielli

Part Number: IWR1443

Hello,

I am using the IWR1443BOOST with mm-Wave SDK 1.0, interfacing with an FPGA. I am using the provided capture demo to bring up the CSI2 interface.

I can reliably observe the correct frame structure as described in datasheet (www.ti.com/.../iwr1443.pdf) Figure 6.5. However I am not sure how to interpret the data within the CSI frame. I have consulted the Technical Reference Manual (www.ti.com/.../swru522b.pdf) Section 13.4.1.1.2 for reference.

Here is what I see

	Lane 0	Lane 1	Lane 2	Lane 3
SYNC	0xb8	0xb8	0xb8	0xb8
DT	0x15	0x03	0x00	0x2c
WC[0:1]	0x12	0x58	0x01	0x14
WC[2:3]	0xfd	0x10	0x0d	0x00
ECC	0x68	0xfb	0x0e	0xd8

The first row is clearly the SoT. However I expect that the next rows should correspond to the Data Type and Word Count fields, but the actual values don't make any sense.

My questions are:

1. Does the data packet follow the MIPI CSI2 standard?

2. How can I interpret the received values in the context of the CSI2 standard?

Thanks for your help.

Regards,

Antonio

over 7 years ago

0 Akash Gondalia over 7 years ago

TI__Guru 50240 points

Hi Antonio,

We'll need a couple of days for an expert to provide an appropriate response.

Cheers,
Akash

0 Antonio Puglielli over 7 years ago in reply to Akash Gondalia

Expert 1025 points

Sounds good, thanks for letting me know Akash.

0 Antonio Puglielli over 7 years ago in reply to Akash Gondalia

Expert 1025 points

Akash,

Could you in the meantime point me toward some documentation describing how the chirp data is multiplexed over the data lanes? For the capture demo, I am using 4 lanes CSI2 and only 1 RX, with 12bits ADC data. I cannot find anywhere a description of how the IQ samples are packed into the CSI2 frame.

Thanks,

Antonio

0 Antonio Puglielli over 7 years ago in reply to Antonio Puglielli

Expert 1025 points

Akash,

No worries - I figured it out.

For anyone else who is looking for this information:
I incorrectly expected the packet header to appear on each lane. However the packet header only appears once in the logical data stream, and is mapped onto the physical lanes according to the multi-lane distribution and merging described in the MIPI standard. Therefore we find that the DT field is 0x2c, the WC is 0x0300, and the ECC is 0x15. The packet data itself is formatted as RAW12 (because 12-bit ADC was selected), and the mapping of RAW12 data into bytes is also described by the MIPI standard.

Antonio

Sensors

Sensors forum

IWR1443: CSI Frame Structure