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Original question:

AWR1243: 40MHz crystal for ARW1243

AWR1243: AWR1243 CASCADED

Siddhartha Shrivastava
Prodigy 80 points
Part Number: AWR1243
Other Parts Discussed in Thread: TDA2SX

Hi,

We are planning for AWR1243 cascaded system for a college project, I have few questions which answered would be great,

1) how many layers of PCB would be optimal for 4 chip cascading?

2) how can we use 4 chips for 360-degree view around the radar?

3) Do the TI provide any SDK for support of cascaded system?

Regards,

Sid

  • 0
    TI__Guru*** 148404 points
    Hi,

    We will release a Cascade Reference Design before the end of the year

    thank you
    Cesar
  • 0 in reply to Cesar
    TI__Mastermind 18470 points
    Hi Sid,

    Answers to your questions below:

    1) All layout recommendations will be released as part of the Cascade reference design released onto ti.com later this year. That is all we can release publically at this time.

    2) Regarding 360-degree view and cascade operation, I don't think this is a good application fit. The primary advantage a design gets from utilizing a cascaded radar solution MIMO and beam-forming across a larger antenna array and phase-noise cancellation at the mixers - resulting in the increased range and resolution performance.

    In a scenario where 4 devices TX and RX are spread across a 360 degree view, none of these functions will be present since there will be minimal field of view overlap. In this case, 4 stand-alone devices would be sufficient for normal operation. Otherwise, 4, 2-device or 4-device, cascade systems may be used if the additional range and resolution of cascade operation are needed.

    If you haven't checked it out already, please see the AWR1243 Cascade application note for a discussion on this topic: www.ti.com/.../swra574a.pdf

    3) Yes, the VisionSDK actually already includes a preview of the reference solution. This can be found here: www.ti.com/.../PROCESSOR-SDK-TDAX

    Please let me know if that answers your questions.

    Thanks,
    Randy
  • 0 in reply to Randy Rosales
    Prodigy 80 points

    Hi Randy,

    Thanks for replying,

    If I go for 4 chip cascaded system, which processor is good for the signal processing for medium range (40 m).

    I have seen TDA3x  in few TI released documents, are they referring to TDA3x EVM?

    or do we have any other option also?

    Regards

    Sid

  • 0 in reply to Siddhartha Shrivastava
    TI__Mastermind 18470 points
    Hi Sid,

    The RadarSDK includes examples for cascade, boot, reset, control and processing which target the TDA2Sx ADAS processors. This is one of the reference designs that will be released later this year.

    The AWR1243 Interface Control Document (ICD) which is included with the AWR1243 Device Firmware Pacakage (DFP) includes documentation of the API necessary for integrating the AWR1243 with any suitable host processor. Your particular radar processing requirements should dictate host processor selection. www.ti.com/.../MMWAVE-DFP. The TDA2Sx RadarSDK cascade demo code implements the ICD defined API.

    Please let me know if that answers your question.

    Thanks,
    Randy