OPT3101: In super - HDR mode

Hi Kevin,

Is this an I2C error or the write succeeds, but the data is not changed when you read it back?

Are you using the EVM? If not could you share some more details on the initialization your are using for the device and your setup?

Best,

Alex

The value was not changed when I read the register, and I2C was written successfully.
The initialization code is written with reference to initialization. Py in EVM. Auto-hdr mode works normally, but when switching to super-hdr mode, after EN_TX1_ON_TX0 in register B9H is written successfully, the bit bit value is read as 0.Writes 0xffffff to the register and reads all zeros. Do you need to enable other enable functions when reading and writing the register?

The following is the configuration of my Super-HDR mode. When running in Super-HDR mode mode, the channel does not switch from TX0 to TX1,Why？ When manually switching to TX1, it can be measured normally.I don't think I entered the comparison register COMPARE_REG1 or COMPARE_REG2 in super-hdr mode.In super-hdr mode, do you need any other configuration besides the following?Does the Sequence STATUS_OUT register need to operate?


//Super-HDR mode config
tg_en = 0;
en_sequencer = 0;
en_processor_values = 0;

illum_dac_l_tx0 = 2;
illum_dac_h_tx0 = 8;
illum_scale_l_tx0 = 0;
illum_scale_h_tx0 = 0;

illum_dac_l_tx1 = 7;
illum_dac_h_tx1 = 28;
illum_scale_l_tx1 = 0;
illum_scale_h_tx1 = 0;

en_tx1_on_tx0 = 1;
en_tx2_on_tx0 = 0;

tg_seq_int_start = 9850;
tg_seq_int_start = 9858;
tg_seq_int_mask_start = AverageFrames - 1; //AverageFrames = 128
tg_seq_int_mask_end = AverageFrames - 1; //AverageFrames = 128

hdr_thr_high = 26000;
hdr_thr_low = 26000/4.8-500;
super_hdr_thr_high = hdr_thr_high + 500;
super_hdr_thr_low = hdr_thr_low - 500;
comp_in_sel = 0;

command0 = 0x108;
command1 = 0xb02;
command2 = 0x100;
command3 = 0xc00;

en_sequencer = 1;
en_processor_values = 1;

tg_en = 1;