LM95071: Minimum High Pulse Width for Chip Select(/CS)

Sadanori Kato

Part Number: LM95071

Hi,

For the chip select(/CS), there is mentioned in LM95071 data sheet that that " The CS signal should be held high for at least one clock cycle (160 ns minimum) between communications" as below.
Is my understanding correct that this minimum high pulse width for /CS doesn't depend on the serial clock period ?

Best regards,
Kato

over 5 years ago

0 Ren Schackmann over 5 years ago

TI__Mastermind 38165 points

Hi Kato-san,

The 160ns note is referencing the clock period specification from page 4.

Thanks,
Ren

0 Sadanori Kato over 5 years ago in reply to Ren Schackmann

Guru 36500 points

Hi Ren-san,

Thank you for your quick response.

The /CS signal should be held high between communications(reading temperature), so does LM95071 work properly regardless of the serial clock period if the high pulse width of /CS is more than 160ns ?

Best regards,
Kato

0 Ren Schackmann over 5 years ago in reply to Sadanori Kato

TI__Mastermind 38165 points

Hi Kato-san,

Yes, the SPI interface will work correctly. The errata is not directly related to SCK period or CS pulse width. See the errata for more information. www.ti.com/.../snla296

Thanks,
Ren

0 Sadanori Kato over 5 years ago in reply to Ren Schackmann

Guru 36500 points

Hi Ren-san,

Thank you for your response.

I understood.

Best regards,
Kato

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LM95071: Minimum High Pulse Width for Chip Select(/CS)