Hello
It is said in document of AWR1243boost that "The lengths of the all high speed lines should be tightly matched to each other (<50 mils mismatch between pairs and <10mils mismatch between P and N lines) to reduce delay mismatch and enable proper data communication".
If i want to design a cascaded AWR1243 radar, should be this matching between high speed data lines (and digital IO) of Master and Slave chips ? Or just apply to any of the chips?
