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AWR1642BOOST: CCS compile error when we porting Clustering/Tracking to mmw demo application

Weks Chen
Intellectual 880 points
Part Number: AWR1642BOOST

Hi team,

SDK: mmwave_sdk_02_00_00_04

Application: mmwave_industrial_toolbox_2_4_0

Question:

We want to porting Clustering/Tracking function from SRR application to mmw demo application.

But we use CSS to debug and met compile error. 

Do you know how to fixed the compile error?

Thanks.

"../c674x_linker.cmd", line 84: error #10099-D: program will not fit into available memory. placement with alignment fails for section ".switch" size 0x215 . Available memory ranges:
L2SRAM_UMAP0 size: 0x20000 unused: 0x21 max hole: 0x7
L2SRAM_UMAP1 size: 0x20000 unused: 0x0 max hole: 0x0
"../c674x_linker.cmd", line 90: error #10099-D: program will not fit into available memory. placement with alignment fails for section ".neardata" size 0xc . Available memory ranges:
L2SRAM_UMAP0 size: 0x20000 unused: 0x21 max hole: 0x7
L2SRAM_UMAP1 size: 0x20000 unused: 0x0 max hole: 0x0
"../c674x_linker.cmd", line 91: error #10099-D: program will not fit into available memory. run placement with alignment fails for section ".stack" size 0x418 . Available memory ranges:
L2SRAM_UMAP0 size: 0x20000 unused: 0x1d max hole: 0x7
L2SRAM_UMAP1 size: 0x20000 unused: 0x0 max hole: 0x0
"../c674x_linker.cmd", line 85: error #10099-D: program will not fit into available memory. run placement with alignment fails for section ".cio" size 0x127 . Available memory ranges:
L2SRAM_UMAP0 size: 0x20000 unused: 0x1d max hole: 0x7
L2SRAM_UMAP1 size: 0x20000 unused: 0x0 max hole: 0x0

  • 0
    TI__Expert 7215 points
    Hi,

    Please note that mmw application is built with all features enabled. You might not need all of them. You can remove certain features and rebuild the code. For e.g. you can remove lvdsStreamCfg specifc code if you don't need the Raw data transfer

    Kindly refer to section 6.9 for memory optimization on mmw application. Since you are getting error for L2 memory, Look for L2 heap reduction in the code.

    Can you also let us know, what is your usecase and why you are not using SRR TI desgin.

    Regards,
    Kaushal
  • 0 in reply to Kaushal Kukkar
    Intellectual 880 points

    Hi Kaushal,

    Thanks, we will check the L2 memory allocation.

    Our use case is BSD+LCW. 

    Because we want to have lots of parameter like chirp/dcRangebias ..etc to adjust our radar, but SRR application uses hard-code define in header files.

    Or do you have better suggestion for us?

    Thanks.

  • 0 in reply to Weks Chen
    TI__Expert 7215 points
    Hi,

    I assume that your chirp and other configuration is fixed so that you can keep in header file. If you have multiple configuration, you can keep multiple configurations and use accordingly.

    I am not sure if you still facing any issue but let us know if you need any specific input.

    Regards,
    Kaushal