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OPT8320: Time Delay on Falling Edge and Rising Edge

Part Number: OPT8320

Hi Team,

We have a timing issue with OPT8320, could you please help? Thanks!

1. What's the time delay between the falling edge of output clock and output data?

2. What's the time delay between the rising edge of output clock and output data?

3. Will the data be sent out on the falling edge or rising edge? 

Best Regards,

Hao

  • Hao,

    The output data toggles on the negative edge and it has to be read out on the positive clock edge in SSI mode as well. We think we need to make an update in the datasheet.

    The delays between falling edge of output clock and data would be a clock to Q delays. It may not affect things much. I think the main problem is the polarity of clock edge at which the data flips.

    Following are a couple of waveforms which show clock and data:

    Channel 1 is data.
    Channel 2 is clock.

    Regards,
    Subhash

  • Hi Subhash,

    Thanks for clarify the output data timing issue.
    Could you please tell me the time delay between the data and the negative edge of the clock?

    Best Regards,
    Hao
  • Hi Subhash,
    Could you please help look at this issue? Thanks!
    Best Regards,
    Hao
  • Hi,

    The output flips at the falling edge of clock. Time delay between the positive edge and data is half clock cycle. Time delay between negative edge and data is clock to Q delay which is negligible. This is apparent in the waveform we have shared.
    I think I said the following in error earlier, "The delays between rising edge of output clock and data would be a clock to Q delays." Please note that this is the correct information.

    Regards,
    Subhash