Tool/software: TI-RTOS
Does frame periodicity refer to the time period between frames or the total period of a frame? For example, let's take the demo configuration:
profileCfg 0 77 429 7 57.14 0 0 70 1 256 5209 0 0 30
chirpCfg 0 0 0 0 0 0 0 1
chirpCfg 1 1 0 0 0 0 0 2
frameCfg 0 1 16 0 100 1 0
In this case the ramp end time is 57.14 microseconds, idle time is 429 microseconds. Therefore, per chirp period is 486.14 microseconds.
TDM is employed here with 2 transmitters, therefore there are 32 chirps total (16 per transmitter) in the frame. Therefore the total chirp time in a frame is 15556.48 microseconds.
Now that a frame is complete, does the system wait for 100 milliseconds - 15.55648 milliseconds or does the system wait for 100 milliseconds before starting the next frame?
Either way, the SDK User Guide suggests "frame[s] should at least have 50% duty cycle and allow enough time for selected UART output to be shipped out". Why is the 50% duty cycle condition not satisfied here?
