AWR1243: LVDS Setup and Hold timing requirements

Hello Rohith,
Why do you suspect setup/hold time issues? Did you probe the data & clk signals to verify if the data is changing very close to the CLK edge?


Regards,
Vivek

Hi Vivek,

I would like to describe the situation more clearly...

The LVDS data capture on my FPGA looks unstable.
The correctness of result is varying build to build. i.e. (Some of the builds will work fine & some builds give me unexpected results).

Since I don't have a clarity on the issue. I would like to cross verify
1. Input delay timing constraints
2. delay element tuning (IDELAY element)

Currently, as a rough estimate, I'm using 35% of Clk_Period/2 as my Input delay (Min and Max). (2.222/2 * 35% = 0.388)
And, I'm not sure whether this constraint is correct or not ??

Could you please give me some direction on this...

I don't have a provision to probe LVDS lines on my custom board.
So, I'm not suspecting any Issue from Interfacing sensor with FPGA. Instead, I would like to cross verify FPGA Circuit

Thanks for your time

Hi Vivek,

Thanks for the reply...

Upon experimentation, we have observed that

for Test patterns, the valid window is ~+/-300ps  

ADC data, the valid window is +/-200ps to +/-250ps

Hi vivek,
For Tighter timing constraints, Can I consider these values as Pessemestic (worst case) numbers.
Do I need to add any clock jitter. If yes, Could you please help me with this number