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AWR1243: Pulse time requirements of Digital Sync Pulse

Part Number: AWR1243


Hi,

I am planning to external sync pulse for my sensor start. i.e., a Hardware trigger for the case of cascading.

I know that it is recommendable as SW trigger for Master and HW trigger for all the 3 slaves. But due to my use case restrictions, I am preferring a HW trigger, which will be provided through a clock buffer to all my four devices.

My question is:

1) What is the pulse requirement of the External Digital Sync? How long should the pulse be high before going low, for proper working

2) Is there are hardware driver requirement, like the pulse driving capability ?? in terms of capacitance or driving power?

if these details are available in any documentation, which I am not able to find, please let me know,

I would be grateful for any help in this direction,

Thanks in advance,

Santhana Raj

  • Hello Santhana,
    The minimum pulse width of the pulse needed is 25nsec and it should less than the frame active period. The same source should be used to trigger all the 4 devices in the cascade configuration.

    The driver capability would depend on your PCB load, effectively the pulse width should be less than 25nsec.

    Regards,
    Vivek