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IWR1443: Power On Sequence (NRESET delay)

Daniel Stracke
Prodigy 40 points
Part Number: IWR1443
Other Parts Discussed in Thread: LP87702

Hello,

I was wondering about the schematics of the IWR1443 EVM, regarding the power-up-sequence.

How is it assured, that the NRESET Signal at the IWR1443 goes high with the needed delay of 3ms after the powerrails are up and stable?

In my view the NRESET is connected to the 3.3V output of the PMIC. As a result of this, the NRESET is set to high together with the rising of the power rails (immediately). Where does the needed delay come from?

Thanks for any explanation

  • 0
    TI__Mastermind 29925 points

    Hello Daniel,

    Our IWR1443 EVM does not actually follow the specified 3ms delay after all of the power rails before NRESET goes high. It is recommend to manually press the NRESET button after power up the EVM.

    Ideally, in your own implementation you would want the NRESET to be controlled by the PGOOD of the PMIC. The LP87524 does not have this capability. You can look at the TIDA-01570 for a proper implementation, where NRESET is controlled by the PGOOD of the LP87702.

    Regards,

    Adrian