Other Parts Discussed in Thread: TLV320AIC3204
Hi,
Based on AMC6821 spec for I2C Data hold time(tHD:DAT) with a 350ns min requirement, our measurement shown that it is around 192ns.
Based on I2C spec (same speed 100kHz), the tHD:DAT is 0us min where Note 3 : A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
Therefore, we would like to know whether AMC6821 has some internal delay and 350ns spec was an internal hold time. Hence, our measured timing of tHD:DAT at 192ns to AMC6821 and if plus additional internal delay of 350nsec, total tHD:DAT = 192+350 = 542ns is correct timing?
Thanks.
Best regards,
Gim Song