Hi,
I am currently working on a project in order to build a new LVDT system using PGA970, achieving 14-bit resolution within a travel range of 2mm. I am testing the working of the PGA970 ADC and the demodulator. I am using SPI protocol to communicate between PGA970 and the MCU and output the LVDT position via the UART (RS232). As the secondary signal is very weak I am constructing an external amplifier in order to amplify it.
The datasheet (pg 42) states that “read data is available on the next SPI transfer. That is, when reading from a memory location, the user must send a subsequent transfer to get the data back. Further, the SPI response contains 16 bits of data. The logic returns data from a 16-bit aligned address; that is SPI reads should not straddle a 16-bit address boundary.”
However, the demodulator register is 32 bits (of which 24bits have the data output). As each SPI read is 16 bits, please advise if it will take 2 cycles to read the demodulator data register. Will the data get distorted between the 2 cycles and is there any solution in order to me to retain the whole 32 bits of data.
Thanks,
Piyusha