AWR1642BOOST: hw trigger of LVDS doesn't work on SRR application

Hi,
When you are copying the LVDS output code snippet from OOB to SRR, make sure that eDMA channel which is configured for LVDS is not being used by SRR application for doing FFT processing.
Make sure that all relative configurations are taken care while copying the code,- CBUFF config, eDMA channel/paramset.

Take a reference from cbuff driver test application to get to know how ADC raw data streaming work which will give you more insight in porting LVDS to SRR.


Regards,
Jitendra

Hi Jitendra,

Thanks for your reply.

We uses SRR mode only and do some modifications. 

But we always get "CBUFF Error Interrupt (DSS_CBUFF_ERR_IRQ)"

We query Cbuff status via CBUFF_control(), and always gets the results

frameStartError = 1;
chirpError = 1;

numErrorInterrupts = 2;

Do you have idea that what we missed? I checked the CBuff test code and still doesn't understand the whole process.

1. copy lvds stream code to SRR

2. Change edma handle to "0" ( Describe on SRR application)

#define CBUFF_EDMA_INSTANCE             (0U)

#define MMW_LVDS_STREAM_EDMA_INSTANCE            CBUFF_EDMA_INSTANCE

3.  HW Session configuration 

/* Populate the configuration: */
sessionCfg.executionMode = CBUFF_SessionExecuteMode_HW;
sessionCfg.edmaHandle = datPathObj->edmaHandle[MMW_LVDS_STREAM_EDMA_INSTANCE];
sessionCfg.allocateEDMAChannelFxn = MmwDemo_LVDSStream_EDMAAllocateCBUFFHwChannel;
sessionCfg.freeEDMAChannelFxn = MmwDemo_LVDSStream_EDMAFreeCBUFFHwChannel;
sessionCfg.frameDoneCallbackFxn = MmwDemo_LVDSStream_HwTriggerFrameDone;
sessionCfg.dataType = CBUFF_DataType_COMPLEX;
datPathObj->cliCfg->adcBufCfg.chInterleave = CBUFF_DataMode_NON_INTERLEAVED;
sessionCfg.u.hwCfg.dataMode = (CBUFF_DataMode)datPathObj->cliCfg->adcBufCfg.chInterleave;

/* Populate the HW Session configuration: */
sessionCfg.u.hwCfg.adcBufHandle = gSrrDSSMCB.adcBufHandle;
sessionCfg.u.hwCfg.numADCSamples = datPathObj->numAdcSamples;
sessionCfg.u.hwCfg.numChirpsPerFrame = datPathObj->numChirpsPerChirpType;
sessionCfg.u.hwCfg.chirpMode = datPathObj->chirpThreshold;
sessionCfg.u.hwCfg.opMode = CBUFF_OperationalMode_CHIRP;

4.

/** @} */
/*! @brief EDMA configuration table for CBUF. */
/** @{*/
#define SRR_CBUFF_EDMA_CH EDMA_TPCC0_REQ_CBUFF_0
#define SRR_CBUFF_EDMA_SHADOW_CH (EDMA_NUM_DMA_CHANNELS + 0U)
#define CBUFF_EDMA_INSTANCE (0U)
/** @}*/

#define SRR_EDMA_TRIGGER_ENABLE 1
#define SRR_EDMA_TRIGGER_DISABLE 0
/** @}*/ /* end defgroup. */

/*************************LVDS streaming EDMA resources*******************************/
#define EDMA_INSTANCE_0 0
#define EDMA_INSTANCE_1 1
/*EDMA instance used*/
#define MMW_LVDS_STREAM_EDMA_INSTANCE CBUFF_EDMA_INSTANCE

/* CBUFF EDMA trigger channels */
#define MMW_LVDS_STREAM_CBUFF_EDMA_CH_0 EDMA_TPCC0_REQ_CBUFF_0
#define MMW_LVDS_STREAM_CBUFF_EDMA_CH_1 EDMA_TPCC0_REQ_CBUFF_1

/*HW Session*/
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_CH_0 EDMA_TPCC0_REQ_FREE_0
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_CH_1 EDMA_TPCC0_REQ_FREE_1
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_CH_2 EDMA_TPCC0_REQ_FREE_2
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_CH_3 EDMA_TPCC0_REQ_FREE_3
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_CH_4 EDMA_TPCC0_REQ_FREE_4
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_CH_5 EDMA_TPCC0_REQ_FREE_5
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_CH_6 EDMA_TPCC0_REQ_FREE_6
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_CH_7 EDMA_TPCC0_REQ_FREE_7
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_CH_8 EDMA_TPCC0_REQ_FREE_8
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_CH_9 EDMA_TPCC0_REQ_FREE_9
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_CH_10 EDMA_TPCC0_REQ_FREE_10
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_CH_11 EDMA_TPCC0_REQ_FREE_11
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_CH_12 EDMA_TPCC0_REQ_FREE_12
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_CH_13 EDMA_TPCC0_REQ_FREE_13
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_CH_14 EDMA_TPCC0_REQ_FREE_14
/*SW Session*/
#define MMW_LVDS_STREAM_SW_SESSION_EDMA_CH_0 EDMA_TPCC0_REQ_FREE_15
#define MMW_LVDS_STREAM_SW_SESSION_EDMA_CH_1 EDMA_TPCC0_REQ_FREE_16

/*shadow*/
/*shadow CBUFF trigger channels*/
#define MMW_LVDS_STREAM_CBUFF_EDMA_SHADOW_CH_0 (EDMA_NUM_DMA_CHANNELS + 12U)
#define MMW_LVDS_STREAM_CBUFF_EDMA_SHADOW_CH_1 (EDMA_NUM_DMA_CHANNELS + 13U)

/*HW Session*/
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_SHADOW_CH_0 (EDMA_NUM_DMA_CHANNELS + 14U)
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_SHADOW_CH_1 (EDMA_NUM_DMA_CHANNELS + 15U)
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_SHADOW_CH_2 (EDMA_NUM_DMA_CHANNELS + 16U)
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_SHADOW_CH_3 (EDMA_NUM_DMA_CHANNELS + 17U)
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_SHADOW_CH_4 (EDMA_NUM_DMA_CHANNELS + 18U)
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_SHADOW_CH_5 (EDMA_NUM_DMA_CHANNELS + 19U)
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_SHADOW_CH_6 (EDMA_NUM_DMA_CHANNELS + 20U)
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_SHADOW_CH_7 (EDMA_NUM_DMA_CHANNELS + 21U)
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_SHADOW_CH_8 (EDMA_NUM_DMA_CHANNELS + 22U)
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_SHADOW_CH_9 (EDMA_NUM_DMA_CHANNELS + 23U)
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_SHADOW_CH_10 (EDMA_NUM_DMA_CHANNELS + 24U)
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_SHADOW_CH_11 (EDMA_NUM_DMA_CHANNELS + 25U)
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_SHADOW_CH_12 (EDMA_NUM_DMA_CHANNELS + 26U)
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_SHADOW_CH_13 (EDMA_NUM_DMA_CHANNELS + 27U)
#define MMW_LVDS_STREAM_HW_SESSION_EDMA_SHADOW_CH_14 (EDMA_NUM_DMA_CHANNELS + 28U)
/*SW Session*/
#define MMW_LVDS_STREAM_SW_SESSION_EDMA_SHADOW_CH_0 (EDMA_NUM_DMA_CHANNELS + 29U)
#define MMW_LVDS_STREAM_SW_SESSION_EDMA_SHADOW_CH_1 (EDMA_NUM_DMA_CHANNELS + 30U)