IWR6843ISK: Power supply questions for the new mmWave radar ICs

Ryan Sarver said:

Is the extra LDO used since it provides lower noise and/or better high-frequency performance than the main PMIC? Is it recommended to use such an LDO in both cases (i.e. 1.3V or 1V operation)?

If you enable LDO bypass in the firmware for the  IWR6843, you can supply 1V directly to the device, if the LDO bypass is disabled you need to supply 1.24V to the device. The 1.24V rails powers key RF blocks and voltage supplied to the rail affect RF performance.

Ryan Sarver said:

Under what conditions is this delay necessary, and is there any documentation available on power-up sequencing?

Section 5.10.1 of the datasheet contains the  Power Supply Sequencing and Reset Timing information

Regards,

Charles O

Hi Charles,

Thanks for your response.

In the timing diagram that you mention it does look like there's a small delay on VIOIN (which would match the load switch on the schematic being on that supply) but unless I'm missing it I don't see what that delay corresponds to? The 'DC Power OK' dashed line doesn't match up with any other signals, so it seems to just indicate that all of the supplies are good.

best,

Ryan

I've found this other thread here, which is about the IWR1443 but it seems it's more or less the same sequence as the IWR6843 from looking at the timing diagram: e2e.ti.com/.../720855

The answer says that the reset pin shouldn't be asserted until at least 3ms after all four power rails have been established. I can't actually find that 3ms anywhere in either the 1443 or 6843 datasheet, but assuming a linear horizontal scale on the timing diagram (Figure 5-1 in the IWR6843 datasheet), it would seem to make sense in relation to the length of the 8ms shown for the MSS boot start.

I was thinking of just adding a capacitor to GND on the nRESET pin to form a simple RC delay with the pull-up that's already there, ensuring at least 3ms before passing the input-high threshold of 1.57V on that pin.

I'm still confused, however, by the design of the IWR6843ISK + MMWAVEICBOOST carrier. Looking at the schematics, there's the load switch, as I had previously mentioned, on the 3V3 (VIOIN) of the ISK, presumably delaying it to be applied about 100uS after the 1V8 supply. So I still don't understand why that's there, or if it's necessary.
And secondly, it seems that the 3ms delay on the reset pin wouldn't be respected, as there's a 10k pull-up is on the MMWAVEICBOOST board with a 100nF cap to ground, providing only 646us delay before passing the 1.57V threshold (if my calculations are correct).

I'm trying to finalize my design and I currently don't have that load switch on there, so I just want to make sure I'm not going to be in for any nasty surprises finding out that actually VIOIN has to be applied after the 1V8.

Hi Charles,

I'm sorry but this isn't answering my question. I understand that some kind of timing sequence needs to be respected, but it's not at all clear from the image in the datasheet what that timing sequence is.

In the hardware checklist I saw mention of the 3ms delay after the lines are stable before asserting the reset, so I'm following that.

But I'm worried by the fact that the datasheet picture appears to show the VDDIN supply activating first, followed by the VIOIN_18 and VIN13RFx supplies at the same time, and finally the VIOIN (see photo below, where I drew in extra lines in red to make my question more clear: