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PGA460: UART to RS232C

Jun Ishida
Expert 5640 points
Part Number: PGA460


Hi team,

The customer is testing PGA460 with below connections.

[PGA460] = [RS232C driver] <=> [MCU]

Currently the customer is facing on the timing issue of data transmission between PGA460 and MCU. According to their testing, it seems the output of RS232C to MCU has unexpected level before the start-bit(negative to positive) with comparing to RS232C standard. Please refer to below image. Do you think why the unexpected level is observed before the start-bit? Do you have any workaround or method to change the positive level before start-bit to negative level by setting from PGA460?

Regards,

Jun

  • 0
    TI__Genius 11015 points
    Jun,

    We have received your question & we will get back with you by early Jan.
  • 0 in reply to Bharat Aravamudhan
    TI__Expert 5640 points

    Hi team,

    The customer added a pull-up to 5V in order to change the level of Tx during idle, then the issue was removed.

    Q1) Are there any problems to pull up the Tx to 5V from the internal circuit point of view?

    Q2) What is the recommended resistor for the pull-up?

    Regards,

    Jun

  • 0 in reply to Jun Ishida
    TI__Mastermind 27950 points
    Hi Jun,

    Adding a pull-up to the TX pin is the only method of forcing the initial start-up idle logic level to a negative equivalent. However, a software workaround is to force an initial junk UART read command at start up to ensure the TX level is idle for the next command, which will can be considered as the first real UART command.

    There is no issue with adding an external pull-up the PGA460's TX pin. Note that the default TX/RX pin logic-high voltage is 3.3V. For a 5V logic level, the PGA460 TEST pin must be pulled high through a 100kOhm resistor to 5V.

    The value of the external TX pin pull-up resistor is user preferred, depending on baud rate (2.4k-115.2k), acceptable sink current, and ensuring the rise-time slew rate does not hinder communicaiton. For most UART systems, I typically start with 10kOhm, then optimize from there.
  • 0 in reply to Akeem Whitehead
    TI__Expert 5640 points
    Hi Akeem-san,

    Thank you so much for the answer.

    Regards,
    Jun
  • 0 in reply to Jun Ishida
    TI__Expert 5640 points
    Hi Akeem-san,

    1) The customer will add the pull-up to TX pin at 5V, but it seems the 5V is from IOREG pin. Is there any problem to use IOREG(5V) to pull-up the TX?

    2) And also, you mentioned that "Note that the default TX/RX pin logic-high voltage is 3.3V. For a 5V logic level, the PGA460 TEST pin must be pulled high through a 100kOhm resistor to 5V." in your answer. If the customer add the pull-up to TX pin at 5V, then does it mean TEST pin should be pulled to 5V with 100kohm in spite of describing 100kohm < Rpu < 500kohm for TEST pin in the datasheet? (100kohm Fixed? 200kohm~500kohm are not recommended?)

    Regards,
    Jun
  • 0 in reply to Jun Ishida
    TI__Expert 5640 points
    Hi Akeem-san,

    Could you provide your answer to me as soon as possible?

    Regards,
    Jun
  • 0 in reply to Jun Ishida
    TI__Mastermind 27950 points
    Hi Jun,

    1) IOREG has a current limit of 50mA. We typically do not recommend to externally load IOREG due to risking the operation of the interface, but if the external load is not a high current load, then it can be managed. Be sure to use a TX pull-up resistor value that does not violate the IOREG specification, and this local workaround should be sufficient.

    2) The R_Test pull-up can be between 100k~500kOhm. The value does not need to be exact. This is simply a weak pull up of TEST to 5V to limit the amount of power consumed by this configuration resistor. An alternative solution is to use a GPIO from an MCU. The GPIO would need to be set high (emulating a pull-up) for 5V TTL operation.