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PGA411-Q1: Masking Faults - OMIZ Fault Questions

Derek Cook
Intellectual 880 points
Part Number: PGA411-Q1

Hello, 

I see a number of faults that can be masked in DEV_CONTROL1. I don't see the ability to mask the OMIZ faults, can you?

I don't really understand the OMIZ faults, because to me it seems they are a more stringent and redundant under and over voltage fault? Could you maybe explain how these faults are different than the under and over voltage faults? It looks like at the widest range, this limits your signal to 2Vpp, whereas if this was disabled, you could have a 4Vpp signal without tripping on the Under and Over voltage (FIZ) faults.

  • 0
    TI__Mastermind 23810 points
    There is no way to mask the OMIZ faults; however, the OMIZ faults do not trigger the fault pin and they do not turn off the exciter or tracking loop. To check the status of the OMIZ faults, you must read the appropriate DEV_STATx register.

    You are right that the OMIZ faults are stricter than the FIZx faults. They are intended to check signal integrity (while FIZx are intended to find short to ground or battery conditions); however, most applications end up not using the OMIZ faults at all.
  • 0 in reply to Clancy Soehren
    Intellectual 880 points
    Hey Clancy thank for the help! Thanks for differentiating the 2!