• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 873 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AWR1642: DCA1000 Ethernet packet delay

Adam Yao94020
Genius 10910 points
Part Number: AWR1642

Hi champion,
   Could you help to check what is the meaning of DCA1000 Ethernet packet delay and why it can cause packet out of order in GUI? Does the delay mean the period of sending ETH packet out of DCA1000?
   In DCA1000 user guide table 19, I find each delay setting has a theoretical throughput value. Could you help to explain how it is calculated?

Thanks,
Adam

  • 0
    TI__Guru 58035 points
    Hello Adam,
    The "packet delay" indicates the intentional delay the DCA1000 adds between two UDP packets. More the delay you add lesser would be the throughput (as indicated in the table 19 of the user guide) , but lesser would be the chances of the PC missing the UDP packets. In UDP protocol there is no guarantee of the packet reception (unlike TCP/IP where there is an ACK etc.). So if the PC is slow or busy doing other tasks it could miss UDP packets. Hence we recommend that if you are seeing packet drops then try increasing the packet delay value.

    Regards,
    Vivek