Hi there,
We are using AWR1243BOOST boards and we want to collect raw ADC data.
We know that MIPI-CSI2 is the recomended way to trasfer ADC data, but at the moment we have to use LVDS and we have to make LVDS working.
We have a doubt on:
- LVDS clock output pins, and
- LVDS clock frequency.
For the first point we noticed that
- LVDS clock is at output debug pins pair N14-N15;
- LVDS frame clock is at output debug pins pair M14-M15;
- LVDS data lines (4 differential pairs) pins are as defined for MIPI-CSI2 case.
Q1: Can you please confirm or comment on the above three bullets?
For the second point, i.e. the LVDS clock frequency measured at N14-N15 pair, we noticed that:
- wrt nominal HSI clock, it is 12 times slower;
- transitions on data lines are only on LVDS clock rising edge, no matter for SDR/DDR configuration.
For example:
- Case 1:
- we set:
- rlDevDataPathCfg_t -> intfSel = 1 (LVDS interface selected)
- rlDevDataPathClkCfg_t -> laneClkCfg = 1b (DDR Clock)
- rlDevDataPathClkCfg_t -> dataRate = 0010b (DDR 450Mbps)
- rlDevHsiClk_t -> hsiClk = 0x5 (DDR 450)
- we get:
- LVDS clock frequency measured at N14-N15 pair equal to 37.5MHz
- transitions on data lines are only on LVDS clock rising edge
- we set:
- Case 2:
- we set:
- rlDevDataPathCfg_t -> intfSel = 1 (LVDS interface selected)
- rlDevDataPathClkCfg_t -> laneClkCfg = 0b (SDR Clock)
- rlDevDataPathClkCfg_t -> dataRate = 0100b (SDR 300Mbps)
- rlDevHsiClk_t -> hsiClk = 0xB (SDR 300)
- we get:
- LVDS clock frequency measured at N14-N15 pair equal to 25MHz
- transitions on data lines are only on LVDS clock rising edge
- we set:
Q2: Can you please confirm or comment on the above measured LVDS clock frequencies?
Thank you in advance for any help.
