AWR1243: AWR1243P Cascading Configuration

Antonio Puglielli

Part Number: AWR1243

Hello,

I have a cascade board with 2 AWR1243P devices (ES3.0, using DFP 1.2).

When attempting to enable the cascade operation of the devices, I see that the CSI2 clock starts up, but no data is sent over the CSI2 interface. There are no FS, FE, LS, or LE packets, and no data packets.

Please see the attached file for a description for how I am programming the device. Note that I am generating an external HW_TRIGGER from my host to trigger both the master and slave devices. I am confident that this HW_TRIGGER is working fine - if I configure the device for single chip mode, I get the expected data output.

Can you please advise what sort of issue might cause this behavior, or what are the recommended debugging steps?

Thanks,
Antonio

Fullscreen OutdoorMaster.txt Download

name: "OutdoorMaster"
dfe_output {
  mode: 1
}
channel {
  rx_mode: 15
  tx_mode: 7
  cascade: 1
}
adc {
  bits: BITS_16
  format: OUTPUT_COMPLEX_1X
}
adc_buffer {
  output_format: COMPLEX
  iq_swap_selector: IQ
  channel_interleave_mode: INTERLEAVE_YES
  chirp_threshold: 1
}
profiles {
  start_frequency: 77.0
  idle_time: 63.0
  adc_start_time: 5.7
  ramp_end_time: 65
  tx_out_power_backoff_code: 0
  tx_phase_shifter: 0.0
  ramp_slope: 60
  tx_start_time: 1
  number_of_adc_samples: 1024
  digital_out_sample_rate: 18750.0
  hpf_corner_1: HPF1_175Khz
  hpf_corner_2: HPF2_350Khz
  rx_gain: 30
  chirps {
    index_start: 0
    index_stop: 0
    start_frequency: 0.0
    ramp_slope: 0.0
    idle_time: 0.0
    adc_start_time: 0.0
    tx_enable: 1
  }
  chirps {
    index_start: 1
    index_stop: 1
    start_frequency: 0.0
    ramp_slope: 0.0
    idle_time: 0.0
    adc_start_time: 0.0
    tx_enable: 2
  }
  chirps {
    index_start: 2
    index_stop: 2
    start_frequency: 0.0
    ramp_slope: 0.0
    idle_time: 0.0
    adc_start_time: 0.0
    tx_enable: 4
  }
  chirps {
    index_start: 3
    index_stop: 5
    start_frequency: 0.0
    ramp_slope: 0.0
    idle_time: 0.0
    adc_start_time: 0.0
    tx_enable: 0
  }
}
frame {
  chirp_start_index: 0
  chirp_end_index: 5
  number_of_loops: 1
  number_of_frames: 0
  frame_periodicity: 1
  frame_trigger_delay: 0
  trigger_mode: TRIGGER_HARDWARE
}

over 6 years ago

0 Cesar over 6 years ago

TI__Guru*** 148594 points

Hi,

We have to check with our cascade hardware designer and get back to you

Thank you
Cesar

0 Antonio Puglielli over 6 years ago in reply to Cesar

Expert 1025 points

Hi Cesar,

Here is some additional info based on my testing today that may be helpful.

- If I configure the master for SOFTWARE_TRIGGER mode, I only ever get one single pulse out of the master, even if it is configured for infinite number of frames. The pulse is about 25ns wide. No data is acquired. I tried searching for magical configurations that would do better, but no luck.

- If I configure the master for HARDWARE_TRIGGER mode, I have played around with a number of timing parameters. For a certain magical set of profile and frame parameters, I can generate approximately one frame's worth of data. I say "one frame's worth" because it seems to occur within a few 100ms of when I send the FRAME_START command and configure the HW_TRIGGER, and never again.

Can you share a cascade programming configuration that is known to work on TI's hardware?

Thanks,
Antonio

0 Randy Rosales over 6 years ago in reply to Antonio Puglielli

TI__Mastermind 18500 points

Hi Antonio,

Based on e-mail communications this was resolved as a BSS/MSS firmware corner-case of setting CALIB_MON_TIME_UNIT to 1 frame in Cascade mode.

Thank you,
-Randy

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AWR1243: AWR1243P Cascading Configuration