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AWR1243: Cascaded AWR1243s do not output data

user4199584
Prodigy 100 points
Part Number: AWR1243

Hi, TI experts

I am working on a project that cascades 4 AWR1243s. The circuit are configured as:

1) the clock inputs of all chips are driven by fanout of a TCXO clock.

2) the CSI-2 outputs are configured as 2-lane, and connected directly to the NVIDIA Jetson TX2, via a adaptor. 

But the board outputs nothing from CSI-2 interface. I tried only master chip with success, either in HWTRIG or SWTRIG mode, but failed with 2-chip or 4-chip cascade configuration.

Here are my questions:

1) Is the above configuration feasible?

2) Which steps should I follow? I tried the steps listed in section 5.22.2 <AWR1xxx_interface_control.pdf>, but with no success.

Qian

PS: Thanks. There is an error in the chip configuration, and the problem is resolved.

  • 0
    TI__Mastermind 18500 points
    Hi Qian,

    Can you please send over a diagram or schematic of the system in question?

    I need to understand your point #2 in more detail. The AWR devices are only meant to operate in cascade mode where one master mode device generates the 20 GHz LO output for one or more slave devices. But, it sounds like you are describing a system where an external FMCW VCO system (not a master mode AWR device) is generating the 20 GHz LO output for the master AND slave devices. Can you please provide more details on this?

    Can you also please list the full configuration procedure as implemented on the nVidia TX2 host device? Can you provide the static configuration, CSI configuration, profile, frame and chirp configuration details?

    With the log presented, which piece of software is generating this? Is this the implementation of the ICD API on the nVidia TX2 host device? I see a point in the log where it appears the rlSetChirpConfig API (AWR_CHIRP_CONF_SET_SB) is returning an error message. This may indicate there is something wrong with the chirp configuration itself. Can you please comment further on that?

    Thank you,
    -Randy



    Thank,
    -Randy
  • 0 in reply to Randy Rosales
    Prodigy 100 points
    Hi, Randy

    Thanks for your reply.
    The FMCW LO signal from FMCW_SYNCOUT pin of master chip is distributed to the FMCW_SYNCIN1 pins of all (master and slave) chips, through a RF amplifier and a 1:4 power divider. There are no external FMCW source. I follow the SWRA574A <AWR1243 Cascade> document strictly.
    Can I reach you in email privately? So I can send the confined details you requires. Also, I need 2~3 days to organize the information, because it's Working Labor Day vacation here.

    Qian
  • 0 in reply to user4199584
    TI__Mastermind 18500 points
    Hi Qian,

    Thank you for clarifying the 20 GHz LO path setup. In general that sounds like a good LO network setup, provided the delay between LO branches is still well matched for both the passive and active portions of the network.

    Before we get into netlist or layout I would like to understand the errors you are seeing from the chirp configuration API that you presented in that log file. As far as I can tell from the log the devices may not even be configured to chirp. Can you please provide more detail on that log and the overall initialization procedure? I understand it was derived from the ICD, but I need to see the whole configuration. Do you see those same errors when running in single-device mode?

    Thank you,
    -Randy
  • 0 in reply to Randy Rosales
    TI__Mastermind 18500 points
    Hi Qian,

    I have not seen a response to my questions in about a week. Please let me know if this is still an open issue.

    Thank you,
    -Randy
  • 0 in reply to Randy Rosales
    Prodigy 100 points

    Hi Randy

    Sorry. We are striving to resolve this problem in these days, and forget to report the progress here.

    The good news is the data of all chips can be read via CSI-2 interface, after a chip-configuration error was fixed. The cascading of AWR1243P is well.

    But  the imaging quality is lower than expected, we are still working on it.

    Thanks for your help.

    Qian