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AWR1243: AWR1243P cascade system

Kshitiz Bansal
Prodigy 180 points
Part Number: AWR1243

I have following queries regarding 1243p cascade system:

1. For a cascade of 1243p chips, there are 2 master pin configurations as shown in the table. Is there a recommended configuration among the 2 based on some thorough evaluation?

2. For the Power splitter used to distributed LO clock, are there some caveats? Should this be present on the PCB itself or we can hook something up externally?

3. Once the cascade HW is set up, what is right FirmWare to be used with the system?

Thanks

  • 0
    TI__Guru 58035 points
    Hello Kshitiz,
    1) Regarding the SYNCIN1/2 , either could be used. Both have same performance. The unused pin should be grounded.
    Regarding the SYNCOUT and CLKOUT , in a 4 chip cascade you would need to use both the pins. In a 2 chip cascade case you could use the SYNCOUT followed by splitter and fed to the slave and back to the master. OR you could use the SYCNOUT to be fed to the slave and use the CLKOUT to be fed back to the master SYCNIN (matched on the board).

    2) The main care about is to make sure the total loss from SYCNOUT/CLKOUT to SYNCIN is less than 7 dB. This includes trace/cable loss, splitter loss, impedance mismatch losses etc.

    3) You can find the firmware in the mmwave DFP package (www.ti.com/.../MMWAVE-DFP).

    Regards,
    Vivek