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Compiler/AWR1843: some questions about L2 memory

brickporter
Intellectual 335 points
Part Number: AWR1843

Tool/software: TI C/C++ Compiler

hi : 

I have some questions about L2 memory.

1) In dss_data_path.c, I on purpose set L2 heapsize as 0x1 (originally, 0x14000U) and others, including L1heap and L3SRAM, remain the same. This is definitely not enough for normal mode. However, I can compile this "wrong" L2 heapsize setting successfully. Is this reasonable?

2) I try to change the length of L2SRAM_UMAP0 in c674x_linker.cmd from l = 0x00020000 to l = 0x00010000. However, after compile, I found that the file xwr18xx_srr_ti_design_dss.map shows the length of L2SRAM_UMAP0 remains  0x00020000.  Is this reasonable?

3) I have read the TMS320C674x DSP Cache USER GUIDE. However, I still cannot distinguish the difference between cache and SRAM. Can you give me some plain explanation?

Thanks

Regards, 

Stan