AWR1243: SYNC_IN edge rate

Antonio Puglielli

Part Number: AWR1243

Hello,

I have a question about the digital SYNC_IN routing on the board for HW_TRIGGER or cascade designs. Is there a spec on the rise/fall time of that signal?

Thanks,
Antonio

over 6 years ago

0 Randy Rosales over 6 years ago

TI__Mastermind 18500 points

Hi Antonio,

There actually is not a spec for this provided in the datasheet. I will check with our IO designers. I'll need a few days to get this information.

Are you seeing any problems on SYNC_IN with respect to trigger slew rate?

Thank you,
-Randy

0 Antonio Puglielli over 6 years ago in reply to Randy Rosales

Expert 1025 points

Hi Randy,

Thanks for checking that for me. I'll look for your response soon.

We don't have any issue, but we're designing a new board and want to check that requirement.

Best,
Antonio

0 Antonio Puglielli over 6 years ago in reply to Antonio Puglielli

Expert 1025 points

Hi Randy,

Any update?

Thanks,
Antonio

0 Randy Rosales over 6 years ago in reply to Antonio Puglielli

TI__Mastermind 18500 points

Hi Antonio,

I am still trying to get our design team to comment on this topic. I will update again in a few days.

Thank you,
-Randy

0 Randy Rosales over 6 years ago in reply to Randy Rosales

TI__Mastermind 18500 points

Hi Antonio,

I am still trying to get our design team to comment on this topic. I will update again in a few days.

Thank you,
-Randy

0 Randy Rosales over 6 years ago in reply to Randy Rosales

TI__Mastermind 18500 points

Hi Antonio,

We do not have a published specification for the minimum slew-rate on these LVCMOS 1.8V/3.3V input buffers. However, I recommend keeping it above 1V/ns. Pulse width minimum timing still needs to account for rise/fall-time relative to VIH/VIL.

Thanks,
-Randy

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AWR1243: SYNC_IN edge rate