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PGA305: PGA305 register

Kazuki Kuramochi
Genius 10665 points
Part Number: PGA305


Hello Professional,

My customer has question for PGA305's register.

Would you provide your answer for below questions?

1. Is Value of DIG_IF_CTRL (100010)  default setting by power up?

2.Do Table19:BRG_CTRL and Table20:BRDG_CTRL same resister? Would you provide default value of BRDG_CTRL?

3.What is deference between Table19, line17 "DIAG_ENABLE" and Table19, Line20 "DIAG_ENABLE"?

4.Could you give me the Rewiting life of internal EEPROM?

5. Are Table20 EEPROM_ARRAY and EEPROM_CACHE mapped to FIGURE21 Memory Cells and Cache?

6. What should we do about DAC output when we only use I2C?

7. We found the consistent between table5 and table6. Table5 said I2C slave address is 0x40/0x42/0x45 when I2CADDR is 0. However Table 6 said 9199919b(0x22) and 0100101b(0x25). Which table is correct?

8. If the register has DI Page/Offset and EEPROM address (i.e. DAC_CONFIG), EEPROM value will change when we write register(DI Page/Offset)? If EEPROM has different value from register(DI page/offset), What is occurring in this situation?

9. 7.3.19.1 said xxxx_GAIN_MSB/LSB and xxxx_OFFSET_BYTE1/BYTE0, however Table 20 indicated xxxx_GAIN_MSB/"MID"/LSB and xxxx_OFFSET_MSB/"MID"/LSB. is this omission of "MID" at 7.3.19.1?

10.  the register name of EEPROM Address(0x40000048) is indicated "PADC_GAIN_MID" on tabel20. But we are sure of this is "PADC_OFFSET_MID". Is this correct?

11. Register Name of EEPROM_PAGE_ ADDRESS indicated ADDR[2:0] at table20. But we think this is ADDR[3:0]. This is because Figure40 said this register has ADDR[3:0]. Is this correct?

I'm looking forward hearing back from you.

Best regards,

Kazuki Kuramochi

  • 0
    TI__Mastermind 31655 points
    Hello Kazuki-san,

    Sorry for the delay as I was out of the office. There are quite a few questions here, so I will take some time to respond. I will get back to you in the next couple of days.

    Regards,
  • 0 in reply to Scott Cummins
    TI__Genius 10665 points
    Hello Scott-san,

    Thank you for your reply.

    I understood your current status.
    However, Customer's status is under designing board now. So he would like to get the answer for below question at least.

    6. What should we do about DAC output when we only use I2C? Are we able to keep open at DAC output if we don't use DAC output?

    I'm waiting for your answer.

    Best regards,
    Kazuki Kuramochi
  • 0 in reply to Kazuki Kuramochi
    TI__Mastermind 31655 points
    Hello Kazuki-san,

    1. DIG_IF_CTRL is 0x42 by default.

    2. Yes, these are the same register. The default value of 0x01 is shown in Table 19.

    3. Like with the BRDG_CTRL these are the same register. Table 19 just shows the default settings for registers that have both digital interface access and are also part of the EEPROM space.

    4. The EEPROM data retention lifespan is specified at 10 years. There is currently no specification for the number of rewrites within that time.

    5. Yes, the EEPROM memory cells and the EEPROM cache from the block diagram are describing the EEPROM array and the EEPROM cache from Table 20.

    6. The output pin can be left floating.

    7. Table 5 is correct.

    8. When the data written through the digital interface address is different from the EEPROM (this must be done with the compensation engine in reset and the device in digital interface mode) the device will use the data in the digital interface address. When the device is placed in compensation mode, the EEPROM data will overwrite what was written in the digital interface mode.

    9. Yes, MID is missing in that description. It is actually part of the PADC_GAIN_xxx registers.

    10. Yes, 0x40000048 should be PADC_OFFSET_MID

    11. Figure 40 is correct. There are 16 EEPROM pages, so 4 bits are needed.

    Regards,
  • 0 in reply to Scott Cummins
    TI__Genius 10665 points
    Hi Scott-san,

    I appreciate your prompt reply.
    I understood.

    Best regards,
    Kazuki Kuramochi