LMP91000: Varying TIA Gain with changes in reference bias setting

Hi Robin, 

I will look into this and get back with you.

Jalen

Robin,

If I am understanding correctly, you are essentially replacing the cell with a precision resistor in which you'd be able to have an expected current output. You are then measuring from the Vout pin to conclude if your TIA gain is the right value, but you are seeing too much error? Is this correct?

Can you share a schematic/diagram of your set up? Can you also share more information on the expected values vs what you are seeing in experiment (also how you are measuring your values)?

Additionally, can you share your register settings with me?

Thanks,

Jalen

The graphics rendering does not show the connection between amplifier A1 inverting input and output.  It is there in the email, but not on the post.

Hey Robin,

As far as datasheet specs the only reference I see to your measurement is that there is a 5% transimpedance gain accuracy and a voltage offset that varies depending on the bias voltage.

Jalen

Robin,

You are correct, the gain number is for the internal resistor. I misspoke, there is a min & max offset depending on the step of your bias voltage which is what the datasheet spec shows.

Can you provide the Vref you are using as well as the output voltages you measure at the Vout pin? 

Have you measured all of the expected values (i.e precision resistors, current through R3) and used the measured values in calculations to be sure?

I believe you could be seeing the sum of different errors such as any variation in the biasing levels along with the offset errors of the amplifier itself.

Jalen

Hello again Jalen,

I have measured the "external" factors of the precision resistor and the reference voltage on our board.  What I have not done, but don;t believe it to be an issue is "characterized"  the amplifier and ADC that are between the 91K and process.  These are well qualified parts in this regime and I have never seen them cause this level of error in any other circuit.  The hopes was to use the tightly speced  (< .+/-0.5% worst case ) bias as the source for injecting a current into the TIA and characterize the gain across all usable settings. When I worse case all "documented" errors, it is less that 1%.   The board circuit actually measures the difference between the Vout and (buffered) C1 pins, so I am, in effect measure the voltage across the gain resistor.  I would be much less concerned. if the error were more constant across the bias settings, but it is not, so now the quandy, how to use this data to "calibrate" the board gain, and more problematic, is this error due to bias errors, or due to actual gain errors?  At the very least, I would appreciate you guidance on how to use this data.  At the very most, I would hope you could offer repeat similar testing there with your resources and report you findings and how to use the data.

This intent here was fold all the board errors of 91k and the remaining board components into one simple measurement taken at several bias settings.  Had the results been more in line with the worst case specs, I would have moved on.  When I add up all the worst case errors I am well under 1% which is more than acceptable.  But at these error levels, I am unsure how to handle the matter appropriately. Let me know if you want to see the board circuit, so you can replicate my worst case calcs and help prove me wrong (or right).  

Thanks again,

Robin

PS, is there any way to post a graphic image from within this web page without using email?  I can figure it out if there is.

Robin - 

I work with Jalen and saw this post - have you tried your experiment with a 1M Ohm resistor in between RE/CE (shorted) and WE instead of a 68.1k? 

I found where at least one other user had done this with success - have not dug into if more current might do what you are seeing yet - but - saw this and thought to share it. 

Please see ==> https://www.zimmerpeacocktech.com/knowledge-base/faq/lmp91000-trouble-shooting/, test 3

Robin - 

Yes - we ordered a sensor to check whole system - looks like it came in, so we should be able to get into this shortly - it's a short week here, but we will try to get to it with some priority. 

sorry for the delay

Hi Robin,

What is the reference voltage you are using?

Can you try adjusting the internal zero to 67% of the reference and see if this helps with the error you see at the different bias levels?

Jalen

Robin,

Can you try adjusting the internal zero to 67% of the reference and see if this helps with the error you see at the different bias levels?

Jalen

Robin,

I believe there could be two sources of the error you see.

1) There is a resistor ladder internally that is not trimmed, so I believe that could be contributing the increased error you see as you lower bias steps.

2) I also believe that you are driving the TIA negative rail too close to GND. If you increase the Internal Zero, you'd allow for my headroom here. 

For these reasons, I;d like to see if adjusting the internal zero gives you a little more linearity.

Jalen

Robin,

Do you have any update to the effective TIA gain at the alternate internal zero settings?

As far as the specs you are concerned about, the TIA gain accuracy is 5%, but this is a typical spec. There is no min or max limit mentioned in the EC table, so it could be possible that your configurations would result in higher error.

Jalen