hi dear supporting team,
customer want to build up a PLL loop with TDC7201+DAC+AMP+OCXO, the interpretation of the phase gap to the control voltage is a hard section. do you have any reference design on this? for an example, if we get 1ns phase gap btw input clk and the loop back clk, how do we know how big voltage needed to generate from the DAC to control the OCXO? Tks a lot!