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TDC7200: TDC7200 delivers implausible TIME1 / SPI transfer is not reasonable

Part Number: TDC7200

Hi all

My TDC7200 is configured as follows:
- calibration is done once at power up, 40 cycles
- 2 stop signals
- 16 averaging mode
- clock counter OVF set (around 3us)
- no coarse counter OVF set
- TDC is clocked with 16MHz

When I now start a measurement, I wait for the TDC interrupt and then read the TIME1, CLOCK_COUNT1, TIME2, CLOCK_COUNT2, TIME3 registers.
Now sometimes I get unreasonably high values in the TIME1 register, which are the around 3.5 times the sysclock (16 MHz) period, which as far as I understood, cannot be (TIME1 can never be longer than 1/sysclock).

Taken a look into the bare SPI communication it looks as follows:

TIME1 is OK, value is 0x29A:

TIME1 is NOT OK, value is 0xF87:

This happens approximately 1 out of 10 times. TIME1 then always has 0x0Fxx, where as 0x02xx would bring the value to a reasonable area.
It seems to me, that the second byte of TIME1 (bits 8 - 11) are corrupted by the TDC somehow. I have no idea how to explain that otherwise. Or am I missing a point?

Cheers Benjo

EDIT:

I found cases where TIME1 has not 0x0Fxx but 0x10XX:

I also checked the 16MHz clock of the TDC and it looks fine. No glitches or noise on the clock.

Cheers Benjo

  • Benjo,

    I will look into this issue and get back with you before Wednesday next week.

  • Hi Bharat

    Thanks for your notice.

    Also, after further thoughts, I think it's unlikely that a faulty clock would cause this behavior as

    1) I use 16 cycle averaging
    2) also TIME2 and TIME3 would equally be affected from time to time

    Waiting for your response

    cheers, benjo

  • Any news on that?

    Cheers, benjo

  • Benjo,

    I have checked the Timex registers using our TDC7200 EVM and I am unable to recreate the scenario wherein the Time1 register is around 3.5 times the sysclock. 

    Also as in Figure 18 in datasheet: TIME1 is occurrence of START edge to first clock edge. TIME2 is occurrence of STOP edge to next clock edge. So if your Time 1 alone is cyclic then ti could be due to the change in START happened closer to first clock edge. Note that the clock timing and your signal timing will be in sync always and that can create this changes.

    Please check if the INTBx pin and Trigg Pins start at the same time in each of the measurement cycle.

  • Hi Bharat,

    Thanks for your answer. However, I think I need some clarification on your statements.

    Bharat Aravamudhan said:
    So if your Time 1 alone is cyclic then ti could be due to the change in START happened closer to first clock edge.


    What do you mean by "change in START closer to first edge"?

    Bharat Aravamudhan said:
    Note that the clock timing and your signal timing will be in sync always and that can create this changes.


    Why will they always be in sync? The TDC clock (16 MHz) is created by an external oscillator and my signal (I guess you mean the START) is created by another microcontroller. So in my opinion, they are not necessarily in sync...

    Bharat Aravamudhan said:
    Please check if the INTBx pin and Trigg Pins start at the same time in each of the measurement cycle.


    Both are outputs, where the TRIGG pin is not connected in my circuit. I only utilize the INTB pin to be informed of a finished multi-cycle average.
    Also in figure 19 of the datasheet, the TRIGG and the INTB signal do not start at the same time.

    Cheers, benjo

  • Benjo,

    Sorry for my late reply. 

    Please note that the clock timing and your signal timing will NOT be in sync always and this will create a difference in the time between the START edge & the subsequent Clock rising edge and hence the Time1 value will change from cycle to cycle. I had this in mind while I typed I had missed the "not". 

    So the variance in the time between the START signal & the Clock edge will provide different values. It is good to check either the INTB or TRIGG pin to check if the cycle of measurement is completed.

    Please note the TDC7200 can measure a ToF of 12ns to 500ns in Mode 1 and between 250ns and 8ms in Mode2.

    Incase the actual ToF that you are measuring is say in the region > 500ns but you have configured the device to measure in Mode1 then the entire Timex values are all cumulatively stored in Time 1 register and this gives us a value of > 1 Clock Period.

    Please verify the time of flight that you are trying to measure and the appropriate Mode is selected.  

  • As already stated, we configured the TDC7200 to wait for two stop signals and use measurement mode 2. Now the problem comes in - the first is just under 500ns, the second is ~1.7us.

    what mesurement mode would you recommend in this case? You think this could cause the problem?

    I'll try to shift the first stop signal beyond 500ns in the meanwhile and let you know.

    UPDATE:

    I shifted the first STOP signal beyond 500ns to ~800ns. The issue remains the same. In this case the TIME1 must clearly not have a value > 1 clock period.
    I also want to note again, the too large TIME1 values happen only approximately 1 out of 10 times. So if it would be the wrong measurement mode, I would assume TIME1 would be affected every time.

  • Benjo,

    As i said before I could not replicate this issue in our setup here with the TDC7200-ZA EVM. The only we get this issue if when the device is configured for say Mode 1 but the actual measured ToF is in Mode 2 vice vera.

    Let me again try with the 2 STOPs scenario that you have mentioned and will get back with you soon.

  • Benjo,

    Yes, I was finally able to replicate your issue of having 2 STOPs (1 STOP @ 800ns & 2STOP @ 1.7us). I use the TDC720x-ZAX EVM for my efforts and using the internal 8MHz clock in this EVM I am unable to replicate your fails even while running the ToF multiple times.

    While you plan to measure 800ns you could use Mode 2 for measurement more however when even you plan to use the 2nd STOP which is at 1.7us you should only use the Mode 2.

    It is pretty tough to debug this issue which occurs once in say 10 times. Please check if the readings are consistent when the average cycle & calibration periods are reduced and external clock is reduced to 8Mhz.