AWR1642: How to config the excess ramping time

Hello team,

Customer is asking how to config the excess ramping time.

In the SRR demo, the ramp end time is same as the ADC_START_TIME + ADC_SAMPLE_POINTS/ADC_SAMPLE_RATE. The excess ramping time is 0. But when customer input this parameter in mmwave studio. It reported an error.

But in document TI CMOS FMCW Radar and Chirp Configuration

it says that the ramp end time is the sum of (a) the ADC start time, (b) the ADC sampling time and (c) the excess ramping time at the end of the ramp.There is no hard requirement on excess ramping time.

But for my understanding, the excess ramping time should be larger than the DFE Filtering Latencies? Is that means the configuration in SRR demo is wrong? How to change it?

SRR demo configuration is shown in below table.

Thanks.

Wesley