Hi,
I was wondering how the AWR1243 senses the SOP pins (AR_TDO_SOP0,POAR0SYNC0OUT0SOP1,AR_PMIC_CLKOUT_SOP2) during boot up as every pin is an output pin.
We want to use this information to create our own cascade solution.
Thanks
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Hi,
I was wondering how the AWR1243 senses the SOP pins (AR_TDO_SOP0,POAR0SYNC0OUT0SOP1,AR_PMIC_CLKOUT_SOP2) during boot up as every pin is an output pin.
We want to use this information to create our own cascade solution.
Thanks
Hi,
In the AWR1243 dataseet, Figure 5-2. describes the "Device Wake-up Sequence". In this sequence, the NRESET de-assertion (GND to VCCIO level transition) is responsible for latching in the starting state of the SOP[2:0] pins. In this diagram a setup/hold time for the SOP pins is indicated relative to the NRESET de-assertion.
Thanks,
-Randy