AWR1843BOOST: When flashing chip, UniFlash hangs at erase command.

Hello,

Is the device in the correct SOP mode? The serial number shouldn't matter.

Regards,

Adrian

Adrian, 

Yes, SOP0 and SOP2 are both enabled.  We have an eval from TI with the switches in the same position and it flashes fine.  Without the switches in the correct position Uniflash was unable to find the com port, but it now finds it fine.  Uniflash then says it sends the command to erase the flash, but freezes at that point and we have to restart Uniflash to do anything else.

Dave

Hello,

What changes did you make between the custom boards and the EVM? Are you able to provide your schematic?

After powering on the board, can you manually toggle the NRST to make sure the SOP state is correctly latched?

Regards,

Adrian

Adrian,

The only change we made to the board was to add custom antennas and adjust schematics to our part numbering system (parts remained the same, just pulled them from our library).

How do I tell if the SOP state is correctly latched?  When pressing the NRST switch (SW2) the LED DS4 turns off and back on when released.  Is that what you mean?

Dave

Any thoughts?

Hello David,

Very sorry for the delay. I am on business travel right now, but will be back in office tomorrow. I will get back to you then.

Yes, after toggling the NRST the SOP state should be latched. This is just to verify that the device is in the correct SOP state before flashing. 

Is it possible to provide the schematic showing the UART connection to the TM4C and then the TM4C connection to the USB?

Regards,

Adrian

Thanks Adrian.  Here are the schematics. PROC051B_Schematics_For_TI.zip

Hello David,

     Schematic doesn't have full information, i.e. Device has boot pins (SOP lines) these need to be defined at correct boot mode option during the NRESET release as shown in the below timing diagram. 

Could you please share how boot mode is configured during the NRESET release. 

After power supplies are stable, Boot configuration pins (PMIC_CLKOUT, SYNC_OUT and TDO) need to have weak pull up/down to device the boot mode prior (3-5msec) NRESET release. Could you please review the device Wake-up sequence requirement is met? 

Thanks and regards,

CHETHAN KUMAR Y.B.

Chethan,

I'm having a hard time linking some of these signals to nets on the board so that I can probe them with an O-scope.  Do you have a list of nets corresponding to the signals listed?

Thanks,

Dave

Hello Dave,

After power supplies are stable, Boot configuration pins also known as SOP lines (PMIC_CLKOUT, SYNC_OUT and TDO) need to be asserted to right boot modes before reset is released.

Is it possible to share how the SOP signals are driven? 

Thanks and regards,

CHETHAN KUMAR Y.B.

Hello Dave,

On the AWR device PMIC_CLKOUT is pin P9, SYNC_OUT is pin G13 and TDO is pin N13. NRESET is pin R3. These pins should all have pullups on your board, you can trace the pins to the pullups on your schematic to see where you should probe.

Regards,

Adrian

Hello Dave, 

Is there any update on the status of your debug?

Regards,

Adrian

Adrian,

Sorry for the lack up updates.  Chethan has been emailing me directly.  After probing the various signals provided I believe them all to be working.  We did find that there was a discrepancy between my schematics and those provided in that when putting my schematics together from the reference designs, I was unaware of the DNP components designated in the variants.  I found 23 resistors, 1 capacitor, and 2 pin connectors that should have been DNP.   After removing them on the test board I used originally there was no change, but Chethan believes the DNP components on board may have fried something.  I plan next to take a board that hasn't ever been powered, remove the DNP's and try again.

Dave