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AWR1243: 1243 cacade

user5378626
Prodigy 170 points
Part Number: AWR1243

Hi

We are using  AWR1243P chips to  achieve cascading  !

In order to  make  the master  work normally , the  master must use its own looped back LO and DIG_SYNC lines to trigger the frame.   Am  I right?

If  I just just use  its own looped back DIG_SYNC but without use its LO (we don't use master to radiate) ,can the master works normally? (I  have  found that In this case the master seems can't do the frame trigger and

there's no chrip signal output from FM_CW_SYNCOUT just  a point Freq signal)

 

  

  • 0
    Prodigy 170 points

    Dear TI expert

    Could you please take a look and reply me on this post.

     we have been eagerly awaiting your reply！

    Thanks a lot!

  • 0 in reply to user5378626
    TI__Mastermind 18500 points

    Hi , 

    Both of these questions are answered in the Cascade App note here: http://www.ti.com/lit/an/swra574a/swra574a.pdf

    Have you read through this application note yet?

    Cascade master mode sets up LO mux paths within the master device such that 1) LO is exported on FMCW_CLKOUT and FMCW_SYNCOUT pins, and 2) LO is required to be received on either FMCW_SYNCIN1 or FMCW_SYNCIN2 (with the unused pin grounded). If this loopback path does not exist, the master does not receive its own LO signal and the chirp will not function. 

    The looped back LO path (master to master) must contain identical routing as the master to slave. This loopback path is intended to be used to balance out the PCB induced delay in the LO signal between master and slave devices. Package and die FMCW_CLKOUT and FMCW_SYNCOUT routing is already balanced. 

    DIG_SYNC should be routed in a similar manner to balance PCB delay between master and slave devices. 

    Thank you,

    -Randy