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CCS/AWR1642: Doesn't SOC_waitAPLLCalibration( ) in soc.c case Infinite loop?

Part Number: AWR1642

Tool/software: Code Composer Studio

Hi,

I'm working with AWR1642. 

I'm still using mmWave SDK 2.1.0.4 because it's LTS version.

I'm considering applying a new function below in 3.3.0.3 to my project.

// C:\ti\mmwave_sdk_02_01_00_04\packages\ti\drivers\soc\src\soc.c

static void SOC_waitAPLLCalibration(SOC_DriverMCB* ptrSOCDriverMCB)
{
    TOPRCMRegs* ptrTopRCMRegs;

    /* Get the TOP RCM registers: */
    ptrTopRCMRegs = ptrSOCDriverMCB->ptrTopRCMRegs;

    /* Wait until APLL clock calibration is done successfully */
    while (CSL_FEXTR(ptrTopRCMRegs->SPARE0, 17U, 16U) != 0x3);
}

However, I think the bold line would loop infinitely if APLL clock calibration were not done.

I wonder if BSS always ensures the successful APLL clock calibration.

If not, should I add some code to escape the line in a few ms.

Please, somebody give some advice to me.

Thank you.

Best regards.

 

  • Hi,

    This API is already available in SDK 2.1 (soc.c). Then why do you need to add this API in your project?

    Could you check this register address (SPARE0: 0xFFFF E1EC) in CCS memory browser? It should be of value 0x000F0028.

    Regards,

    Jitendra

  • Thank you for replying. 

    I was not able to find this API in SDK 2.1.0.4.

    As far as I understand, the mmWave 2.1.0.4 has SOC_checkBLAPLLCalibration instead of SOC_waitAPLLCalibration in soc.c,

    and SOC_checkBLAPLLCalibration was modified to SOC_waitAPLLCalibration in SDK 3.3.0.3.
    The release note in SDK 3.3.0.3 says this modification as below.
    • For better reliability, SOC_init will wait for RadarSS to lock the APLL instead of relying on ROM BL based lock mechanism.

    I'm considering applying the function because of reliability.

    I know the register is changed. 

    However,  it could fail and get stuck in the infinite loop.

    Does BSS change the register always? Does it guarantee?

    Thank you.

    Regards,

  • Hi,

    You need call SOC_waitAPLLCalibration function after SOC_unhaltBSS function, where ptrTopRCMRegs->SPARE0 (0xFFFFE1EC) should have required bit set [17:16] to 1.

    With the BSS Unhalt these bits must set to 1.

    What is the register (0xFFFFE1EC) when you call SOC_unhaltBSS function?

    Regards,

    Jitendra