• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 29 subscribers
  • Views 178 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TIDEP-01012: CSI-2 feed

Errol Leon6
Expert 5850 points
Part Number: TIDEP-01012

Hello team,

My customer had a question on the CSI-2 feed from the radar chip and wondering if there was an advantage the FPGA processing EVM versus directly consuming the data from the CSI-2 feed. 

Are there any concerns with the direct approach?

Thanks!
Errol 

  • 0
    TI__Mastermind 18500 points

    Hi Errol,

    There is no concern. All that is required is a 4-lane, MIPI D-PHY CSI2 receiver per AWRx device. The TI TDA2x family does not have this capability natively, so it was necessary to utilize a CSI2 to parallel port bridge (in FPGA) in our case. 

    Thank you,

    -Randy