PGA460: Delay requirements between SPI reads of different addresses

Kevin Lannen

Part Number: PGA460

Hi,

We can have up to 3 PGA460s on the same SPI bus. At system startup we do a read of the eepromCrc register (0x2B) for each possible address and then check the checksum of the result to ensure that there is a device plugged in.

If we have two plugged in, the second one never gets recognized unless we put a delay between the end of the first read and the start of reading the second one. I looked all through the datasheet and could not find a specification for what the minimum delay is between the end of one read and the start of the next read on a different address. Is this spec published? I do not like putting random delays into code unless I can back them up with a spec as for why they are needed.

Thanks,

Kevin

over 5 years ago

0 Akeem Whitehead over 5 years ago

TI__Mastermind 27950 points

Hi Kevin,

Another user has encountered a similar error: https://e2e.ti.com/support/sensors/f/1023/t/851524

I am checking with our digital design team if there is a minimum timeout or delay value required for a bus interface topology when using individual address commands.

Thanks for bringing this to our attention.

0 Akeem Whitehead over 5 years ago in reply to Akeem Whitehead

TI__Mastermind 27950 points

Hi Kevin,

After checking with the digital design team, there should be no need to add milliseconds worth of delay between UART commands on a bus. If you are able to, the next step of debug would be for you to provide a data log of all the UART commands you are sending on the UART bus with time stamps for each for us to review the data and timing sequences. You could also use a digital logic analyzer to capture this information.

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PGA460: Delay requirements between SPI reads of different addresses