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AWR1243: AWR1243P cascade system

Kshitiz Bansal
Prodigy 180 points
Part Number: AWR1243

Hi,

My question is with reference to following application note: http://www.ti.com/lit/an/swra574a/swra574a.pdf

My questions are:

1. What is the purpose of the mux highlighted by the red arrow? In other words, what signal controls its input? Does it change at all across master and slave?

2. Setting a chip as master allows feeding the LO back to master to match delay. Does this mean that if I set both the boards as master, then based on the 2nd mux's pin select state (which seems to be the same in both slave and master), the cascade would still work? If not, then what are the exact difference between master and slave config apart from sending the reference clock at the output?

Thanks and regards,

Kshitiz

  • 0
    TI__Guru 58035 points

    Hello Kshitiz,

    >>1. What is the purpose of the mux highlighted by the red arrow? In other words, what signal controls its input? Does it change at all across master and slave?

    The same device can be used in single chip mode, master mode or slave mode. Based on the configuration the device firmware sets the appropriate mux setting. You do not have to explicitly set it yourself, its automatically taken care of within the firmware.

    >> 2. Setting a chip as master allows feeding the LO back to master to match delay. Does this mean that if I set both the boards as master, then based on the 2nd mux's pin select state (which seems to be the same in both slave and master), the cascade would still work? If not, then what are the exact difference between master and slave config apart from sending the reference clock at the output?

    It is not recommended to keep both the devices in master mode. In slave mode the internal 20Ghz source is complete disabled, which is not the case in master. Also the digital synchronization is different in slave and master configuration

    Regards,
    Vivek