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Original question:

AWR1243: It seems that CSI-2 ports can be configured into normal LVDS ports. I wonder if I can get certain specifications...

AWR1243: LVDS Protocol understanding

Nishant G
Expert 1600 points
Part Number: AWR1243
Other Parts Discussed in Thread: AWR1443
Hello,
For AWR1243, in the datasheet, pin M15 and M14 is described as differential debug port 1. (shown below)
lvds.png
However, the same pins in AWR1443 datasheet is described as LVDS_FRMCLK. I believe the differential debug port 1 is same as LVDS_FRMCLK as the behaviour of AWR1243 and AWR1443 is similar. Could you please confirm it with your team? 
My second question is related to the LVDS protocol issues. I have seen repeatedly in the forum that TI mentions that it is not good for production. Could you please tell me the reason why it can't be used for production purposes? Is their any signal integrity issue compared with CSI-2?
I look forward to your reply. Thank you!
Best Regards,
Nishant
  • 0
    TI__Guru 58035 points

    Hello Nishant,

    You are right, the pins M15 and M14 LVDS_FRMCLK differential signal pins. The reason the LVDS interface is suggested as a debug interface (hence the name suggesting HS_DEBUG) is that we do not qualify or run production tests on the LVDS interface.

    Regards,

    Vivek 

  • 0 in reply to Vivek Dham
    Expert 1600 points

    Hello Vivek,

    Thank you for confirming it. Could you also explain to me why the LVDS is not qualified for production? If we have LVDS_FRMCLK generated from AWR1243, wouldn't it be able to distinguish individual frames? My concern is that CSI-2 was originally developed for camera specific applications, so I prefer to try LVDS for my application. I have listed few of the questions regarding LVDS below:

    1. One of the problems I see in  lvds is the lack of synchronization between data and clk lines in LVDS which can be addressed if delay is adjusted properly. Am I right?

    2. The other reason I found is the additional heating on LVDS lines compared to CSI-2. However, does this mean that while using LVDS, the Tx Power of antenna is reduced as compared to when using CSI-2? or is it just extra power power being drawn by the AWR1243 for a given Tx power?

    3. For debug and testing, for hardware design, what additional precaution should I take while routing LVDS lines compared to CSI-2? Will routing it as100ohm differential impedance to the processor be sufficient to meet the requirement?

    I look forward to your answer and thank you for your help again.

    Best Regards,

    Nishant

  • 0 in reply to Nishant G
    TI__Guru 58035 points

    Hello Nishant,

    The reason this is not qualified in production is because we intended it to be only for debug purpose. CSI2 is a standard protocol and can be universally used with standard processors.  LVDS does not have any standard protocol definition and the compatibility on the TX and Rx needs to be built.

    CSi2 is not used for camera data only, its been used for many high speed data transfers. Since the protocol and standard are well defined by MIPI there are typically no compatibility issues.

    Coming to your question :

     >>1. One of the problems I see in  lvds is the lack of synchronization between data and clk lines in LVDS which can be addressed if delay is adjusted properly. >>Am I right?

    Could you clarify what you mean by lack of synchronization ? Are you seeing a large skew between the CLK and DATA lines? From the device side these are well matched, if they leangth matched on the PCB you should not see much skew.

    >>2. The other reason I found is the additional heating on LVDS lines compared to CSI-2. However, does this mean that while using LVDS, the Tx Power of >>antenna is reduced as compared to when using CSI-2? or is it just extra power power being drawn by the AWR1243 for a given Tx power?

    I assume you are referring to higher current consumption in LVDS mode as compared to CSI mode. This is independent of TX o/p. Basically LVDS does not have the low power modes like CSI , it also used a larger common mode. So the current consumption of the LVDS IP is larger than CSI IP. About 200mW or so.

    >>3. For debug and testing, for hardware design, what additional precaution should I take while routing LVDS lines compared to CSI-2? Will routing it >>as100ohm differential impedance to the processor be sufficient to meet the requirement?

    The impedance should be 100 ohms differential. Also the lines need to be well length matched to each other.

    Regards,
    Vivek

  • 0 in reply to Vivek Dham
    Expert 1600 points

    Thanks Vivek for the detailed answer.

    Yes, I was referring to the skew between the data and clock lines. But like you said, if I match it properly, this shouldn't be an issue then.

    Best Regards,

    Nishant