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AWR1243: LVDS ADC data 0 and shifted

Daniel Zehnder
Intellectual 330 points
Part Number: AWR1243

Hi,

We are running automated test that quires one frame at the time from the sensor and stops after each frame to save the data. And repeats that over and over. In our case we have 8 chirps with 512 samples each. At a random point in time during this test the sensor will have suddenly all 0 data on all four lanes and then the data will come back but is now shifted relative to the start of the chirp, which then will have a discontinuity in all subsequent chirps.

LVDS data form Sensor:

From T to T is one chirp. Signals from top to bottom: Valid, Frame Clock, LVDS data 0, LVDS data 1, LVDS data 2, LVDS data 3.  

Looking at waveform from this data it looks like this:

Chirp 1 is fine. Then chirp 2-6 is 0 data. Then at the end chirp 7 data is coming out but shifted relative to the start of the chirp. Data above from another chip is fine (this is a four chip radar system). 

Then when a new frame is acquired the data stays shifted by the same amount and it stays shifted for all subsequent frames.

What could cause this issue? Or how could we recover from this so that data is aligned again with the start of the chirps?

Thanks,

Daniel

  • 0
    TI__Guru 58035 points

    Hello Daniel,

    Are you using your own system to capture the LVDS data coming from the AWr1243 device? It seems to be an issue on the capture side.

    Regards,

    Vivek

  • 0 in reply to Vivek Dham
    TI__Guru 58035 points

    Hello Daniel,

    I assume the plots you have shared are the values captured by the FPGA receiving the LVDs data. The figures are not very clear but in the first figure the top row is the DATA VALID signal , I am unable to see any toggles in the Data Valid signal inbetween the chirps.  At the end of every chirp, before the next chirp data starts, the datavalid signal should be going low. Have you probed the LVDS signals on an oscilloscope directly to see if this is happening? Also are you not using the Frame clkout signal in your FPGA to capture the data? Typically we use the Frame clock signal to align the sample boundary, but that would depend on the implementation you have on your capture system.

    Could you confirm your chirp configuration and LVDs configuration allows sufficient time for the data transfer to happened before the next chirp starts? Basically the time needed to send out the ADC data over LVDS interface should be lesser than the chirp time.

    regards,

    Vivek 

  • 0 in reply to Vivek Dham
    Intellectual 330 points

    Vivek,

    I assume the plots you have shared are the values captured by the FPGA receiving the LVDs data.

    Yes.

    The figures are not very clear but in the first figure the top row is the DATA VALID signal , I am unable to see any toggles in the Data Valid signal inbetween the chirps.  At the end of every chirp, before the next chirp data starts, the datavalid signal should be going low.

    Since I have limited capture memory inside the FPGA I only capture data when the VALID signal is high. That's why it doesn't show any gaps. But there are gaps between the chirps.

    Have you probed the LVDS signals on an oscilloscope directly to see if this is happening?

    No yet. But I will be doing that shortly.

    Also are you not using the Frame clkout signal in your FPGA to capture the data? Typically we use the Frame clock signal to align the sample boundary, but that would depend on the implementation you have on your capture system.

    No I don't use Frame clock. I count the bits that I receive and this seems to work fine.

    Could you confirm your chirp configuration and LVDs configuration allows sufficient time for the data transfer to happened before the next chirp starts? Basically the time needed to send out the ADC data over LVDS interface should be lesser than the chirp time.

    Yes.

    Thanks,

    Daniel

  • 0 in reply to Daniel Zehnder
    TI__Guru 58035 points

    Hello Daniel,

    I would be helpful if you can explain how  have you isolated the issue being at the LVDS output vs capture issue in the FPGA.

    We have not observed any shift happening in the middle of a chirp from the AWR side.  The complete chirp data being missed out could happen if the data transfer out time over LVDS is not sufficient.

    Regards,

    Vivek